| Age | Commit message (Expand) | Author |
|---|
| 2018-12-11 | cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctor | Tony Gutierrez |
| 2018-12-03 | cpu: Change raw pointers to STL Containers | Rekai Gonzalez-Alberquilla |
| 2018-11-16 | cpu: Fix the usage of const DynInstPtr | Rekai Gonzalez-Alberquilla |
| 2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
| 2018-06-11 | misc: Substitute pointer to Request with aliased RequestPtr | Giacomo Travaglini |
| 2017-10-13 | cpu-o3: Check predication before the SQ size for a debug print | Nikos Nikoleris |
| 2017-10-13 | cpu-o3: Avoid early checker verification for store conditionals | Nikos Nikoleris |
| 2016-12-21 | cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3 | Arthur Perais |
| 2015-08-10 | mem, cpu: Add assertions to snoop invalidation logic | Stephan Diestelhorst |
| 2015-07-19 | cpu: Fix LLSC atomic CPU wakeup | Krishnendra Nathella |
| 2015-12-04 | cpu: fix unitialized variable which may cause assertion failure | Pau Cabre |
| 2015-09-15 | cpu, o3: consider split requests for LSQ checksnoop operations | Hongil Yoon |
| 2015-05-05 | mem, cpu: Add a separate flag for strictly ordered memory | Andreas Sandberg |
| 2014-12-02 | cpu, o3: Ignored invalidate causing same-address load reordering | Marco Elver |
| 2014-12-02 | cpu: Move packet deallocation to recvTimingResp in the O3 CPU | Stephan Diestelhorst |
| 2014-10-16 | arch: Use shared_ptr for all Faults | Andreas Hansson |
| 2014-09-20 | base: Clean up redundant string functions and use C++11 | Andreas Hansson |
| 2014-05-13 | mem: Refactor assignment of Packet types | Curtis Dunham |
| 2014-09-03 | cpu: Fix cache blocked load behavior in o3 cpu | Mitch Hayenga |
| 2014-09-03 | cpu: Change writeback modeling for outstanding instructions | Mitch Hayenga |
| 2014-06-21 | o3: split load & store queue full cases in rename | Binh Pham |
| 2014-05-31 | style: eliminate equality tests with true and false | Steve Reinhardt |
| 2014-04-01 | cpu: Fix case where o3 lsq could print out uninitialized data | Mitch Hayenga |
| 2014-03-25 | cpu: o3: lsq: Fix TSO implementation | Marco Elver |
| 2014-01-24 | cpu: Add support for instructions that zero cache lines. | Ali Saidi |
| 2014-01-24 | cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo... | Ali Saidi |
| 2014-01-24 | base: add support for probe points and common probes | Matt Horsnell |
| 2014-01-24 | mem: track per-request latencies and access depths in the cache hierarchy | Matt Horsnell |
| 2013-10-17 | cpu: add consistent guarding to *_impl.hh files. | Matt Horsnell |
| 2013-10-17 | cpu: Put in assertions to check for maximum supported LQ/SQ size | Faissal Sleiman |
| 2013-07-18 | mem: Set the cache line size on a system level | Andreas Hansson |
| 2013-02-15 | o3: fix tick used for renaming and issue with range selection | Matt Horsnell |
| 2013-01-07 | cpu: Rewrite O3 draining to avoid stopping in microcode | Andreas Sandberg |
| 2013-01-07 | cpu: Fix O3 LSQ debug dumping constness and formatting | Andreas Sandberg |
| 2013-01-07 | o3: Fix issue with LLSC ordering and speculation | Ali Saidi |
| 2012-12-06 | o3 cpu: remove some unused buggy functions in the lsq | Nathanael Premillieu |
| 2012-08-22 | Packet: Remove NACKs from packet and its use in endpoints | Andreas Hansson |
| 2012-06-05 | O3: Clean up the O3 structures and try to pack them a bit better. | Ali Saidi |
| 2012-05-01 | MEM: Separate requests and responses for timing accesses | Andreas Hansson |
| 2012-04-14 | MEM: Remove the Broadcast destination from the packet | Andreas Hansson |
| 2012-03-30 | MEM: Introduce the master/slave port sub-classes in C++ | William Wang |
| 2012-03-09 | CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable | Geoffrey Blake |
| 2012-01-31 | CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 | Geoffrey Blake |
| 2012-01-28 | O3 CPU LSQ: Implement TSO | Nilay Vaish |
| 2011-09-27 | O3: Tidy up some DPRINTFs in the LSQ. | Gabe Black |
| 2011-09-27 | Faults: Replace calls to genMachineCheckFault with M5PanicFault. | Gabe Black |
| 2011-09-26 | LSQ: Moved a couple of lines to enable O3 + Ruby | Nilay Vaish |
| 2011-09-22 | event: minor cleanup | Steve Reinhardt |
| 2011-09-13 | LSQ: Only trigger a memory violation with a load/load if the value changes. | Ali Saidi |
| 2011-07-31 | O3: Implement memory mapped IPRs for O3. | Gabe Black |
