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extra : convert_revision : 19fce78a19b27b7ccb5e3653a64b46e6d5292915
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extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
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extra : convert_revision : f9c78e86b60c3085cd95b1b4e132205e0ef584dd
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into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/system.cc:
Hand Merge
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extra : convert_revision : d5e0c97caebb616493e2f642e915969d7028109c
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extra : convert_revision : 58e960e5019f944c7ec5606e4b8c93ce42330719
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start fetching from.
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extra : convert_revision : a2e4845fedf113b5a2fd92d3d28ce5b006278103
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split execute instructions and miscregs aliasing with integer registers.
src/arch/isa_parser.py:
Rearranged things so that classes with more than one execute function treat operands properly.
1. Eliminated the CodeBlock class
2. Created a SubOperandList
3. Redefined how InstObjParams is constructed
To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions.
Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays.
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/branch.isa:
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa/formats/nop.isa:
src/arch/sparc/isa/formats/priv.isa:
src/arch/sparc/isa/formats/trap.isa:
Rearranged to work with new InstObjParam scheme.
src/cpu/o3/sparc/dyn_inst.hh:
Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays.
src/cpu/simple/base.hh:
Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays.
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extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
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extra : convert_revision : 974e91a960251a35d5ebb76c7e6c7ac330339896
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extra : convert_revision : 599650c408667bb1b8db20a6847b9e697f7b49e4
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extra : convert_revision : dcd1d2a64fd91aded15c8c763a78b4eebf421870
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extra : convert_revision : 7a4aed238d437dbb2cc5946b3045d53697070a27
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setSyscallReturn function rather than having a duplicated one.
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extra : convert_revision : 1e83ef629a7fd143f2e35e68abaa56f81d6b9d9e
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here that shouldn't be in the architecture specific DynInst classes.
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extra : convert_revision : dad0d7191acf773c16dc3ed9dd911f5e8bfc08b3
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src/arch/sparc/process.cc:
MachineBytes doesn't exist any more.
src/arch/sparc/regfile.cc:
Add in the miscRegFile for good measure.
src/cpu/o3/isa_specific.hh:
Add in a section for SPARC
src/cpu/o3/sparc/cpu.cc:
src/cpu/o3/sparc/cpu.hh:
src/cpu/o3/sparc/cpu_builder.cc:
src/cpu/o3/sparc/cpu_impl.hh:
src/cpu/o3/sparc/dyn_inst.cc:
src/cpu/o3/sparc/dyn_inst.hh:
src/cpu/o3/sparc/dyn_inst_impl.hh:
src/cpu/o3/sparc/impl.hh:
src/cpu/o3/sparc/params.hh:
src/cpu/o3/sparc/thread_context.cc:
src/cpu/o3/sparc/thread_context.hh:
Sparc version of this file.
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extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
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