gem5 - gem5

Age	Commit message (Expand)	Author
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black
2007-08-13	Move the "translate" member functions back into the base o3 class.	Gabe Black
2007-07-30	Fix problem with tracer not being initialized.	Gabe Black
2007-07-26	X86: Fix argument register indexing.	Gabe Black
2007-07-23	Major changes to how SimObjects are created and initialized. Almost all	Nathan Binkert
2007-05-12	Make sure all addresses used in syscalls are truncated to 32 bits. Actually -...	Gabe Black
2007-04-14	Add support for microcode and pull out the special branch delay slot handling...	Gabe Black
2007-04-04	Updates for other ISA cpu_builders.	Kevin Lim
2007-04-02	Fix up SPARC's CPU builder to match changes to Alpha's CPU builder.	Kevin Lim
2007-03-07	I missed a couple of WithEffects, this should do it	Ali Saidi
2007-03-07	MiscReg->MiscRegNoEffect, MiscRegWithEffect->MiscReg	Ali Saidi
2007-01-29	Fixed a warning about an unused variable.	Gabe Black
2007-01-27	Merge zizzer:/bk/newmem	Gabe Black
2007-01-26	eliminate cpu checkInterrupts bool, it is redundant and unnecessary.	Lisa Hsu
2006-12-16	Made branch delay slots get squashed, and passed back an NPC and NNPC to star...	Gabe Black
2006-12-16	Changes to the isa_parser and affected files to fix an indexing problem with ...	Gabe Black
2006-12-07	Compilation fixes	Gabe Black
2006-12-06	Use the renamed register index, rather than the flattened one.	Gabe Black
2006-12-06	Got rid of some typedefs and moved the tlbs into the base o3 cpu.	Gabe Black
2006-12-06	Don't panic, but this needs to be fixed.	Gabe Black
2006-12-06	Make syscalls flatten their register indices, and also call into the ISA's se...	Gabe Black
2006-12-06	Get rid of some typedefs which were hardly used, and move some stuff back her...	Gabe Black
2006-11-24	Initial changes to get O3 working with SPARC	Gabe Black