gem5 - gem5

Age	Commit message (Collapse)	Author
2006-12-16	Made branch delay slots get squashed, and passed back an NPC and NNPC to ↵	Gabe Black
	start fetching from. --HG-- extra : convert_revision : a2e4845fedf113b5a2fd92d3d28ce5b006278103
2006-12-16	Changes to the isa_parser and affected files to fix an indexing problem with ↵	Gabe Black
	split execute instructions and miscregs aliasing with integer registers. src/arch/isa_parser.py: Rearranged things so that classes with more than one execute function treat operands properly. 1. Eliminated the CodeBlock class 2. Created a SubOperandList 3. Redefined how InstObjParams is constructed To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions. Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays. src/arch/sparc/isa/formats/basic.isa: src/arch/sparc/isa/formats/branch.isa: src/arch/sparc/isa/formats/integerop.isa: src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/isa/formats/nop.isa: src/arch/sparc/isa/formats/priv.isa: src/arch/sparc/isa/formats/trap.isa: Rearranged to work with new InstObjParam scheme. src/cpu/o3/sparc/dyn_inst.hh: Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays. src/cpu/simple/base.hh: Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. --HG-- extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
2006-12-07	Compilation fixes	Gabe Black
	--HG-- extra : convert_revision : 974e91a960251a35d5ebb76c7e6c7ac330339896
2006-12-06	Use the renamed register index, rather than the flattened one.	Gabe Black
	--HG-- extra : convert_revision : 599650c408667bb1b8db20a6847b9e697f7b49e4
2006-12-06	Got rid of some typedefs and moved the tlbs into the base o3 cpu.	Gabe Black
	--HG-- extra : convert_revision : dcd1d2a64fd91aded15c8c763a78b4eebf421870
2006-12-06	Don't panic, but this needs to be fixed.	Gabe Black
	--HG-- extra : convert_revision : 7a4aed238d437dbb2cc5946b3045d53697070a27
2006-12-06	Make syscalls flatten their register indices, and also call into the ISA's ↵	Gabe Black
	setSyscallReturn function rather than having a duplicated one. --HG-- extra : convert_revision : 1e83ef629a7fd143f2e35e68abaa56f81d6b9d9e
2006-12-06	Get rid of some typedefs which were hardly used, and move some stuff back ↵	Gabe Black
	here that shouldn't be in the architecture specific DynInst classes. --HG-- extra : convert_revision : dad0d7191acf773c16dc3ed9dd911f5e8bfc08b3
2006-11-24	Initial changes to get O3 working with SPARC	Gabe Black
	src/arch/sparc/process.cc: MachineBytes doesn't exist any more. src/arch/sparc/regfile.cc: Add in the miscRegFile for good measure. src/cpu/o3/isa_specific.hh: Add in a section for SPARC src/cpu/o3/sparc/cpu.cc: src/cpu/o3/sparc/cpu.hh: src/cpu/o3/sparc/cpu_builder.cc: src/cpu/o3/sparc/cpu_impl.hh: src/cpu/o3/sparc/dyn_inst.cc: src/cpu/o3/sparc/dyn_inst.hh: src/cpu/o3/sparc/dyn_inst_impl.hh: src/cpu/o3/sparc/impl.hh: src/cpu/o3/sparc/params.hh: src/cpu/o3/sparc/thread_context.cc: src/cpu/o3/sparc/thread_context.hh: Sparc version of this file. --HG-- extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4