gem5 - gem5

Age	Commit message (Expand)	Author
2008-10-12	Get rid of old RegContext code.	Gabe Black
2008-10-09	O3: Generalize the O3 CPU object so it isn't split out by ISA.	Gabe Black
2008-07-01	Remove delVirtPort() and make getVirtPort() only return cached version.	Ali Saidi
2008-07-01	Make the cached virtPort have a thread context so it can do everything that a...	Ali Saidi
2007-11-15	add microPC stuff back in. got deleted on changeset propragation somehow.	Korey Sewell
2007-11-15	Get MIPS simple regression working. Take out unecessary functions "setShadowS...	Korey Sewell
2007-11-13	Add in files from merge-bare-iron, get them compiling in FS and SE mode	Korey Sewell
2007-08-26	Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.	Gabe Black
2007-03-07	MiscReg->MiscRegNoEffect, MiscRegWithEffect->MiscReg	Ali Saidi
2006-12-07	Compilation fixes	Gabe Black
2006-12-06	Got rid of some typedefs and moved the tlbs into the base o3 cpu.	Gabe Black
2006-11-29	Change the connecting of the physPort and virtPort to the memory object below...	Kevin Lim
2006-11-19	Update Virtual and Physical ports.	Kevin Lim
2006-11-07	Moved the switched version of kernel_stats.hh back to kern, and moved the bas...	Gabe Black
2006-11-01	Adjustments for the AlphaTLB changing to AlphaISA::TLB and changing register ...	Gabe Black
2006-07-23	This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...	Korey Sewell
2006-07-07	Fix so that O3CPU doesnt segfault on exit.	Korey Sewell
2006-07-03	Fix for FS O3CPU compile ... missing forward class declaration/header file af...	Korey Sewell
2006-06-30	Make O3CPU model independent of the ISA	Korey Sewell