| Age | Commit message (Expand) | Author |
|---|
| 2014-01-24 | arch, cpu: Add support for flattening misc register indexes. | Ali Saidi |
| 2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
| 2013-01-07 | cpu: Unify SimpleCPU and O3 CPU serialization code | Andreas Sandberg |
| 2013-01-07 | cpu: Implement a flat register interface in thread contexts | Andreas Sandberg |
| 2013-01-07 | cpu: rename the misleading inSyscall to noSquashFromTC | Ali Saidi |
| 2012-08-28 | Clock: Add a Cycles wrapper class and use where applicable | Andreas Hansson |
| 2012-05-26 | CPU: Merge the predecoder and decoder. | Gabe Black |
| 2012-05-25 | Decode: Make the Decoder class defined per ISA. | Gabe Black |
| 2012-03-19 | gcc: Clean-up of non-C++0x compliant code, first steps | Andreas Hansson |
| 2012-03-09 | CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable | Geoffrey Blake |
| 2012-02-24 | MEM: Make port proxies use references rather than pointers | Andreas Hansson |
| 2012-01-31 | Merge with head, hopefully the last time for this batch. | Gabe Black |
| 2012-01-31 | CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5 | Geoffrey Blake |
| 2012-01-30 | Merge with main repository. | Gabe Black |
| 2012-01-30 | MEM: Clean-up of Functional/Virtual/TranslatingPort remnants | Andreas Hansson |
| 2012-01-28 | Merge with the main repo. | Gabe Black |
| 2012-01-17 | MEM: Add port proxies instead of non-structural ports | Andreas Hansson |
| 2011-10-31 | SE/FS: Make the functions available from the TC consistent between SE and FS. | Gabe Black |
| 2011-10-30 | SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs. | Gabe Black |
| 2011-10-16 | SE/FS: Include getMemPort in FS. | Gabe Black |
| 2011-10-16 | SE/FS: Build/expose vport in SE mode. | Gabe Black |
| 2011-10-16 | CPU: Make physPort and getPhysPort available in SE mode. | Gabe Black |
| 2011-09-09 | Decode: Pull instruction decoding out of the StaticInst class into its own. | Gabe Black |
| 2011-04-15 | includes: sort all includes | Nathan Binkert |
| 2010-10-31 | ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors. | Gabe Black |
| 2010-09-13 | CPU: Get rid of the now unnecessary getInst/setInst family of functions. | Gabe Black |
| 2009-11-04 | o3: get rid of unused physmem pointer | Steve Reinhardt |
| 2009-09-23 | arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh | Nathan Binkert |
| 2009-07-08 | Registers: Get rid of the float register width parameter. | Gabe Black |
| 2009-07-08 | Registers: Add an ISA object which replaces the MiscRegFile. | Gabe Black |
| 2009-05-12 | inorder-bpred: edits to handle non-delay-slot ISAs | Korey Sewell |
| 2009-04-15 | Get rid of the Unallocated thread context state. | Steve Reinhardt |
| 2009-04-08 | tlb: Don't separate the TLB classes into an instruction TLB and a data TLB | Gabe Black |
| 2009-02-27 | Processes: Make getting and setting system call arguments part of a process o... | Gabe Black |
| 2009-01-19 | thread_context: move getSystemPtr so SE mode can get to it. | Nathan Binkert |
| 2008-11-04 | get rid of all instances of readTid() and getThreadNum(). Unify and eliminate | Lisa Hsu |
| 2008-11-02 | Add in Context IDs to the simulator. From now on, cpuId is almost never used, | Lisa Hsu |
| 2008-11-02 | make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered | Lisa Hsu |
| 2008-10-12 | Get rid of old RegContext code. | Gabe Black |
| 2008-10-09 | O3: Generalize the O3 CPU object so it isn't split out by ISA. | Gabe Black |
| 2008-07-01 | Remove delVirtPort() and make getVirtPort() only return cached version. | Ali Saidi |
| 2008-07-01 | Make the cached virtPort have a thread context so it can do everything that a... | Ali Saidi |
| 2007-11-15 | add microPC stuff back in. got deleted on changeset propragation somehow. | Korey Sewell |
| 2007-11-15 | Get MIPS simple regression working. Take out unecessary functions "setShadowS... | Korey Sewell |
| 2007-11-13 | Add in files from merge-bare-iron, get them compiling in FS and SE mode | Korey Sewell |
| 2007-08-26 | Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. | Gabe Black |
| 2007-03-07 | *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg | Ali Saidi |
| 2006-12-07 | Compilation fixes | Gabe Black |
| 2006-12-06 | Got rid of some typedefs and moved the tlbs into the base o3 cpu. | Gabe Black |
| 2006-11-29 | Change the connecting of the physPort and virtPort to the memory object below... | Kevin Lim |
