gem5 - gem5

Age	Commit message (Expand)	Author
2010-08-23	ISA: Get rid of old, unused utility functions cluttering up the ISAs.	Gabe Black
2010-08-23	O3: Skipping mem-order violation check for uncachable loads.	Min Kyu Jeong
2010-08-23	ARM: Improve printing of uop disassembly.	Min Kyu Jeong
2010-08-23	CPU: Make Exec trace to print predication result (if false) for memory instru...	Min Kyu Jeong
2010-08-23	ARM: mark msr/mrs instructions as SerializeBefore/After	Min Kyu Jeong
2010-08-23	O3: Handle loads when the destination is the PC.	Min Kyu Jeong
2010-08-23	ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.	Min Kyu Jeong
2010-08-13	CPU: Add readBytes and writeBytes functions to the exec contexts.	Gabe Black
2010-07-22	LSQ Unit: After deleting part of a split request, set it to NULL so that it	Timothy M. Jones
2010-07-22	O3CPU: Fix a bug where stores in the cpu where never marked as split.	Timothy M. Jones
2010-07-22	O3CPU: O3's tick event gets squashed when it is switched out. When repeatedly	Timothy M. Jones
2010-06-23	O3ThreadContext: When taking over from a previous context, only assert that	Timothy M. Jones
2010-02-26	cpu_models: get rid of cpu_models.py and move the stuff into SCons	Nathan Binkert
2010-02-12	O3PCU: Split loads and stores that cross cache line boundaries.	Timothy M. Jones
2009-11-04	o3: get rid of unused physmem pointer	Steve Reinhardt
2009-09-26	O3: Add flag to control whether faulting instructions are traced.	Steve Reinhardt
2009-09-26	O3: Mark fetch stage as active if it faults.	Steve Reinhardt
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2009-08-01	Fix setting of INST_FETCH flag for O3 CPU.	Steve Reinhardt
2009-07-25	o3-smt: enforce numThreads parameter for SMT SE mode	Korey Sewell
2009-07-08	Get rid of the unused get(Data\|Inst)Asid and (inst\|data)Asid functions.	Gabe Black
2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black
2009-07-08	Registers: Get rid of the float register width parameter.	Gabe Black
2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black
2009-06-04	move: put predictor includes and cc files into the same place	Nathan Binkert
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2009-05-17	includes: sort includes again	Nathan Binkert
2009-05-17	types: Move stuff for global types into src/base/types.hh	Nathan Binkert
2009-05-12	inorder-o3: allow both to compile together	Korey Sewell
2009-05-12	inorder-bpred: edits to handle non-delay-slot ISAs	Korey Sewell
2009-04-19	Mem: Change isLlsc to isLLSC.	Gabe Black
2009-04-19	Memory: Rename LOCKED for load locked store conditional to LLSC.	Gabe Black
2009-04-18	o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ...	Korey Sewell
2009-04-17	o3, inorder: fix FS bug due to initializing ThreadState to Halted.	Steve Reinhardt
2009-04-15	o3: handle fetch with no active threads correctly.	Steve Reinhardt
2009-04-15	o3: fix {read,set}ArchFloatReg* functions.	Steve Reinhardt
2009-04-15	ThreadState: initialize status to Halted in constructor.	Steve Reinhardt
2009-04-15	Get rid of the Unallocated thread context state.	Steve Reinhardt
2009-04-08	tlb: More fixing of unified TLB	Nathan Binkert
2009-04-08	tlb: Don't separate the TLB classes into an instruction TLB and a data TLB	Gabe Black
2009-03-07	stats: fix duplicate statistics names.	Nathan Binkert
2009-03-05	stats: Fix all stats usages to deal with template fixes	Nathan Binkert
2009-03-04	O3: Make numThreads error message more helpful.	Steve Reinhardt
2009-02-27	Processes: Make getting and setting system call arguments part of a process o...	Gabe Black
2009-02-26	CPA: Add code to automatically record function symbols as CPU executes.	Ali Saidi
2009-02-25	ISA: Replace the translate functions in the TLBs with translateAtomic.	Gabe Black
2009-02-25	CPU: Get rid of translate... functions from various interface classes.	Gabe Black
2009-02-10	CPU: Prepare CPU models for the new in-order CPU model.	Korey Sewell
2009-01-24	cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep.	Nathan Binkert