| Age | Commit message (Collapse) | Author |
|---|
|
|
|
When each load or store is sent to the LSQ, we check whether it will cross a
cache line boundary and, if so, split it in two. This creates two TLB
translations and two memory requests. Care has to be taken if the first
packet of a split load is sent but the second blocks the cache. Similarly,
for a store, if the first packet cannot be sent, we must store the second
one somewhere to retry later.
This modifies the LSQSenderState class to record both packets in a split
load or store.
Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA
to indicate whether unaligned memory accesses are allowed. This is used
throughout the changed code so that compiler can optimise away code dealing
with split requests for ISAs that don't need them.
|
|
|
|
When enabled, faulting instructions appear in the trace twice
(once when they fault and again when they're re-executed).
This flag is set by the Exec compound flag for backwards compatibility.
|
|
Otherwise if the rest of the pipeline is idle then
fault will never propagate to commit to be handled,
causing CPU to deadlock.
|
|
|
|
Get rid of misc.py and just stick misc things in __init__.py
Move utility functions out of SCons files and into m5.util
Move utility type stuff from m5/__init__.py to m5/util/__init__.py
Remove buildEnv from m5 and allow access only from m5.defines
Rename AddToPath to addToPath while we're moving it to m5.util
Rename read_command to readCommand while we're moving it
Rename compare_versions to compareVersions while we're moving it.
--HG--
rename : src/python/m5/convert.py => src/python/m5/util/convert.py
rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
|
|
It's still broken in inorder.
Also enhance DPRINTFs in cache and physical memory so we
can see more easily whether it's getting set or not.
|
|
|
|
|
|
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.
--HG--
rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh
rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh
rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh
rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh
rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
|
|
|
|
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.
|
|
--HG--
rename : src/cpu/2bit_local_pred.cc => src/cpu/pred/2bit_local.cc
rename : src/cpu/o3/2bit_local_pred.hh => src/cpu/pred/2bit_local.hh
rename : src/cpu/btb.cc => src/cpu/pred/btb.cc
rename : src/cpu/o3/btb.hh => src/cpu/pred/btb.hh
rename : src/cpu/ras.cc => src/cpu/pred/ras.cc
rename : src/cpu/o3/ras.hh => src/cpu/pred/ras.hh
rename : src/cpu/tournament_pred.cc => src/cpu/pred/tournament.cc
rename : src/cpu/o3/tournament_pred.hh => src/cpu/pred/tournament.hh
|
|
|
|
|
|
--HG--
rename : src/sim/host.hh => src/base/types.hh
|
|
allow InOrder and O3CPU to be compiled at the same time: need to make branch prediction filed shared by both models
|
|
Changes so that InOrder can work for a non-delay-slot ISA like Alpha. Typically, changes have to do with handling misspeculated branches at different points in pipeline
|
|
|
|
|
|
stage was not setting the predicted PC correctly or passing that information back to fetch correctly
|
|
For some reason o3 FS init() only called initCPU if the thread state
was Suspended, which was no longer the case. There's no apparent
reason to check, so I whacked the test completely rather than
changing the check to Halted.
The inorder init() was also updated to be symmetric, though the
previous code was just a fancy no-op.
|
|
This situation can arise now on the first fetch cycle after
the last active thread is halted. It seems easy enough to
deal with when it happens rather than trying to avoid it.
|
|
Register indices were not being calculated properly.
|
|
This provides a common initial status for all threads independent
of CPU model (unlike the prior situation where CPUs initialized
threads to inconsistent states).
This mostly matters for SE mode; in FS mode, ISA-specific startupCPU()
methods generally handle boot-time initialization of thread contexts
(since the right thing to do is ISA-dependent).
|
|
Basically merge it in with Halted.
Also had to get rid of a few other functions that
called ThreadContext::deallocate(), including:
- InOrderCPU's setThreadRescheduleCondition.
- ThreadContext::exit(). This function was there to avoid terminating
simulation when one thread out of a multi-thread workload exits, but we
need to find a better (non-cpu-centric) way.
|
|
|
|
|
|
This generally requires providing a more meaningful name() function for a
class.
|
|
|
|
|
|
object.
|
|
|
|
|
|
|
|
Some new functions and forward declarations are necessary to make things work
|
|
Make interrupts use the new wakeup method, and pull all of the interrupt
stuff into the cpu base class so that only the wakeup code needs to be updated.
I tried to make wakeup, wakeCPU, and the various other mechanisms for waking
and sleeping a little more sane, but I couldn't understand why the statistics
were changing the way they were. Maybe we'll try again some day.
|
|
|
|
There was really no reason that it should be FS only.
|
|
|
|
This is to prevent the assertion from firing if you have a large multicore.
Also make sure that it's not compiled in when NDEBUG is defined
|
|
redundancies with threadId() as their replacement.
|
|
the primary identifier for a hardware context should be contextId(). The
concept of threads within a CPU remains, in the form of threadId() because
sometimes you need to know which context within a cpu to manipulate.
|
|
across the subclasses. generally make it so that member data is _cpuId and
accessor functions are cpuId(). The ID val comes from the python (default -1 if
none provided), and if it is -1, the index of cpuList will be given. this has
passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard
switch.
|
|
comments.
|
|
|
|
Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.
Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.
Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
|
|
|
|
x86's Interrupts object.
|
