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path: root/src/cpu/o3
AgeCommit message (Expand)Author
2009-11-04o3: get rid of unused physmem pointerSteve Reinhardt
2009-09-26O3: Add flag to control whether faulting instructions are traced.Steve Reinhardt
2009-09-26O3: Mark fetch stage as active if it faults.Steve Reinhardt
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
2009-08-01Fix setting of INST_FETCH flag for O3 CPU.Steve Reinhardt
2009-07-25o3-smt: enforce numThreads parameter for SMT SE modeKorey Sewell
2009-07-08Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.Gabe Black
2009-07-08Registers: Add a registers.hh file as an ISA switched header.Gabe Black
2009-07-08Registers: Get rid of the float register width parameter.Gabe Black
2009-07-08Registers: Add an ISA object which replaces the MiscRegFile.Gabe Black
2009-06-04move: put predictor includes and cc files into the same placeNathan Binkert
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
2009-05-12inorder-o3: allow both to compile togetherKorey Sewell
2009-05-12inorder-bpred: edits to handle non-delay-slot ISAsKorey Sewell
2009-04-19Mem: Change isLlsc to isLLSC.Gabe Black
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2009-04-18o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ...Korey Sewell
2009-04-17o3, inorder: fix FS bug due to initializing ThreadState to Halted.Steve Reinhardt
2009-04-15o3: handle fetch with no active threads correctly.Steve Reinhardt
2009-04-15o3: fix {read,set}ArchFloatReg* functions.Steve Reinhardt
2009-04-15ThreadState: initialize status to Halted in constructor.Steve Reinhardt
2009-04-15Get rid of the Unallocated thread context state.Steve Reinhardt
2009-04-08tlb: More fixing of unified TLBNathan Binkert
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2009-03-07stats: fix duplicate statistics names.Nathan Binkert
2009-03-05stats: Fix all stats usages to deal with template fixesNathan Binkert
2009-03-04O3: Make numThreads error message more helpful.Steve Reinhardt
2009-02-27Processes: Make getting and setting system call arguments part of a process o...Gabe Black
2009-02-26CPA: Add code to automatically record function symbols as CPU executes.Ali Saidi
2009-02-25ISA: Replace the translate functions in the TLBs with translateAtomic.Gabe Black
2009-02-25CPU: Get rid of translate... functions from various interface classes.Gabe Black
2009-02-10CPU: Prepare CPU models for the new in-order CPU model.Korey Sewell
2009-01-24cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep.Nathan Binkert
2009-01-21o3cpu: give a name to the activity recorder for better tracingNathan Binkert
2009-01-19thread_context: move getSystemPtr so SE mode can get to it.Nathan Binkert
2008-12-06eventq: use the flags data structureNathan Binkert
2008-11-10O3CPU: Make the instcount debugging stuff per-cpu.Clint Smullen
2008-11-04get rid of all instances of readTid() and getThreadNum(). Unify and eliminateLisa Hsu
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
2008-10-23s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos inLisa Hsu
2008-10-21style: Use the correct m5 style for things relating to interrupts.Nathan Binkert
2008-10-20O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...Ali Saidi
2008-10-12Get rid of old RegContext code.Gabe Black
2008-10-12Turn Interrupts objects into SimObjects. Also, move local APIC state into x86...Gabe Black
2008-10-11CPU: Eliminate the simPalCheck funciton.Gabe Black
2008-10-11CPU: Eliminate the hwrei function.Gabe Black