| Age | Commit message (Expand) | Author |
|---|
| 2019-05-12 | still cannot run fence+ift...hitsb | Iru Cai |
| 2019-05-12 | finally runs dhrystone | Iru Cai |
| 2019-05-12 | only spec load when hit | Iru Cai |
| 2019-05-11 | try not expose if L1 hitis-ift-cachehit | Iru Cai |
| 2019-04-22 | fix the violation checking for IFT+fence | Iru Cai |
| 2019-04-17 | add a trackBranch option | Iru Cai |
| 2019-04-17 | IFT for fence scheme | Iru Cai |
| 2019-04-16 | track instruction after tainted branches | Iru Cai |
| 2019-04-15 | Add IFT debug flags | Iru Cai |
| 2019-04-12 | add IEW DPRINTF | Iru Cai |
| 2019-04-12 | keep time to expose as original scheme when inst->needPostFetch() | Iru Cai |
| 2019-04-12 | add IFT options | Iru Cai |
| 2019-04-10 | clear taint when previous branch resolved | Iru Cai |
| 2019-04-08 | we need to ++loadsToVLD when (!inst->readyToExpose() && inst->needPostFetch()) | Iru Cai |
| 2019-04-08 | implement taint propagation | Iru Cai |
| 2019-04-03 | check loads using tainted registers, set USL dst as tainted | Iru Cai |
| 2019-04-02 | methods to set taint | Iru Cai |
| 2019-04-02 | add taint map | Iru Cai |
| 2019-04-02 | print load inst | Iru Cai |
| 2019-04-01 | fix getvaddr nullptr stuff, add a non-spec load printingis-rebase11-LSQUnit | Iru Cai |
| 2019-03-21 | Request::getVaddr() | Iru Cai |
| 2019-03-20 | invisispec-1.0 source | Iru Cai |
| 2018-12-11 | cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctor | Tony Gutierrez |
| 2018-12-03 | cpu: Change raw pointers to STL Containers | Rekai Gonzalez-Alberquilla |
| 2018-11-28 | cpu,arch-arm: Initialise data members | Rekai Gonzalez-Alberquilla |
| 2018-11-27 | arch, base, cpu, gpu, mem: Replace assert(0 or false with panic. | Gabe Black |
| 2018-11-16 | cpu: Fix the usage of const DynInstPtr | Rekai Gonzalez-Alberquilla |
| 2018-08-10 | cpu: Removed unnecessary file reg_class_impl.hh | Bradley Wang |
| 2018-07-24 | cpu-o3: Missing freeing the heads of DepGraph in IQ squashing | Hanhwi Jang |
| 2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
| 2018-06-11 | misc: Substitute pointer to Request with aliased RequestPtr | Giacomo Travaglini |
| 2018-03-27 | cpu: Remove ExtMachInst typedefs from the O3 CPU model. | Gabe Black |
| 2018-03-06 | scons: Switch from the print statement to the print function. | Gabe Black |
| 2018-02-20 | cpu-o3: Don't add non-speculative mem barriers to the IQ twice | Andreas Sandberg |
| 2018-01-10 | style: change C/C++ source permissions to noexec | BKP |
| 2018-01-10 | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. | Gabe Black |
| 2018-01-09 | cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults. | Gabe Black |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-12-22 | cpu: Use the generic nop static inst instead of decoding the arch version. | Gabe Black |
| 2017-12-13 | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. | Gabe Black |
| 2017-12-05 | cpu: Add support for CMOs in the cpu models | Nikos Nikoleris |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-11-28 | cpu-o3: Add missing vector stat initializers | Andreas Sandberg |
| 2017-11-21 | cpu, cpu, sim: move Cycle probe update | Jose Marinho |
| 2017-11-21 | cpu-o3: Prevent cpu from suspending if it is already draining | Nikos Nikoleris |
| 2017-11-20 | pwr: Adds logic to enter power gating for the cpu model | Anouk Van Laer |
| 2017-11-14 | cpu, probe: Fix elastic trace register dependency | Radhika Jagtap |
| 2017-10-19 | cpu-o3: Add M5_VAR_USED to variable | Jason Lowe-Power |
| 2017-10-13 | cpu-o3: Check predication before the SQ size for a debug print | Nikos Nikoleris |
| 2017-10-13 | cpu-o3: Avoid early checker verification for store conditionals | Nikos Nikoleris |
