gem5 - gem5

Age	Commit message (Expand)	Author
2011-08-16	O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively.	Gabe Black
2011-08-14	O3: When squashing, restore the macroop that should be used for fetching.	Gabe Black
2011-08-14	O3: Add a pointer to the macroop for a microop in the dyninst.	Gabe Black
2011-08-13	O3: At the end of an instruction, force fetchAddr to something sensible.	Gabe Black
2011-08-09	O3: Stop using the current macroop no matter why you're leaving it.	Gabe Black
2011-08-09	O3: When waiting to handle an interrupt, let everything drain out.	Gabe Black
2011-08-07	O3: Get rid of the unused addToRemoveList function.	Gabe Black
2011-08-07	O3: Let squashed and deferred instructions issue.	Gabe Black
2011-08-02	O3: Get rid of the raw ExtMachInst constructor on DynInsts.	Gabe Black
2011-07-31	O3: Implement memory mapped IPRs for O3.	Gabe Black
2011-07-30	O3: Fix corner case squashing into the microcode ROM.	Gabe Black
2011-07-15	O3: Create a pipeline activity viewer for the O3 CPU model.	Giacomo Gabrielli
2011-07-10	O3: Fix up pipelining icache accesses in fetch stage to function properly	Geoffrey Blake
2011-07-10	O3: Make sure fetch doesn't go off into the weeds during speculation.	Ali Saidi
2011-06-10	o3: missing newlines on some dprintfs	Korey Sewell
2011-06-02	scons: rename TraceFlags to DebugFlags	Nathan Binkert
2011-05-23	O3: Fix offset calculation into storeQueue buffer for store->load forwarding	Geoffrey Blake
2011-05-23	O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.	Geoffrey Blake
2011-05-23	O3: Fix issue with interrupts/faults occuring in the middle of a macro-op	Geoffrey Blake
2011-05-13	O3: Fix an issue with a load & branch instruction and mem dep squashing	Geoffrey Blake
2011-05-04	O3: Remove assertion for case that is actually handled in code.	Ali Saidi
2011-05-04	O3: Fix a small corner case with the lsq hazard detection logic.	Ali Saidi
2011-04-20	stats: one more name violation	Nathan Binkert
2011-04-19	stats: rename stats so they can be used as python expressions	Nathan Binkert
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: fix up code after sorting	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-04-04	ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.	Ali Saidi
2011-04-04	ARM: Cleanup implementation of ITSTATE and put important code in PCState.	Ali Saidi
2011-04-04	CPU: Remove references to memory copy operations	Ali Saidi
2011-04-04	O3: Tighten memory order violation checking to 16 bytes.	Ali Saidi
2011-03-17	O3: Send instruction back to fetch on squash to seed predecoder correctly.	Ali Saidi
2011-03-17	O3: Cleanup the commitInfo comm struct.	Ali Saidi
2011-03-17	Mem: Fix issue with dirty block being lost when entire block transferred to n...	Ali Saidi
2011-03-17	O3: Fix unaligned stores when cache blocked	Ali Saidi
2011-02-25	O3CPU: Fix iqCount and lsqCount SMT fetch policies.	Timothy M. Jones
2011-02-23	O3: When a prefetch causes a fault, don't record it in the inst	Ali Saidi
2011-02-23	O3: If there is an outstanding table walk don't let the inst queue sleep.	Ali Saidi
2011-02-23	ARM: Do something for ISB, DSB, DMB	Ali Saidi
2011-02-23	ARM: Fix bug that let two table walks occur in parallel.	Ali Saidi
2011-02-23	O3: Fix bug when a squash occurs right before TLB miss returns.	Ali Saidi
2011-02-13	O3: Fetch from the microcode ROM when needed.	Gabe Black
2011-02-13	O3: Fix GCC 4.2.4 complaint	Ali Saidi
2011-02-11	O3: Fix pipeline restart when a table walk completes in the fetch stage.	Giacomo Gabrielli
2011-02-11	O3: Enhance data address translation by supporting hardware page table walkers.	Giacomo Gabrielli
2011-02-06	mcpat: Adds McPAT performance counters	Joel Hestness
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2011-02-02	O3: Fix a style bug in O3.	Gabe Black
2011-02-01	X86: Add L1 caches for the TLB walkers.	Gabe Black
2011-01-18	O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.	Matt Horsnell