gem5 - gem5

Age	Commit message (Expand)	Author
2012-08-21	Clock: Make Tick unsigned and remove UTick	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-07-27	checker: make checker cpu id match its host's cpu id	Anthony Gutierrez
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-07-09	Fix: Address a few benign memory leaks	Andreas Hansson
2012-06-29	O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.	Nathanael Premillieu
2012-06-05	ISA: Back-out NoopMachInst as a StaticInstPtr change.	Ali Saidi
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-06-04	ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.	Gabe Black
2012-05-26	CPU: Merge the predecoder and decoder.	Gabe Black
2012-05-25	Decode: Make the Decoder class defined per ISA.	Gabe Black
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-30	CPU: Unify initMemProxies across CPUs and simulation modes	Andreas Hansson
2012-03-21	O3: Fix sizing of decode to rename skid buffer.	Andrew Lukefahr
2012-03-21	O3: Fix size of skid buffer between fetch and decode when widths are different	Brian Grayson
2012-03-19	gcc: Clean-up of non-C++0x compliant code, first steps	Andreas Hansson
2012-03-11	O3: Add fatal when fetchWidth > Impl::MaxWidth.	Brian Grayson
2012-03-09	O3/Ozone: Eliminate dead code counting software prefetch insts	Geoffrey Blake
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-03-02	CPU: Check that the interrupt controller is created when needed	Andreas Hansson
2012-03-01	x86: Fix switching of CPUs	Nilay Vaish
2012-02-24	MEM: Make port proxies use references rather than pointers	Andreas Hansson
2012-02-24	CPU: Round-two unifying instr/data CPU ports across models	Andreas Hansson
2012-02-13	BPred: Fix RAS to handle predicated call/return instructions.	Mrinmoy Ghosh
2012-02-13	BP: Fix several Branch Predictor issues.	Mrinmoy Ghosh
2012-02-12	cpu: add separate stats for insts/ops both globally and per cpu model	Anthony Gutierrez
2012-02-12	mem: Add a master ID to each request object.	Ali Saidi
2012-02-10	O3 CPU: Improve handling of delayed commit flag	Nilay Vaish
2012-02-10	O3 CPU: Strengthen condition for handling interrupts	Nilay Vaish
2012-02-10	O3 CPU: Provide the squashing instruction	Nilay Vaish
2012-02-10	O3 Fetch: Check if PC is pointing to Microcode ROM	Nilay Vaish
2012-02-07	Faults: Turn off arch/faults.hh	Gabe Black
2012-01-31	Merge with head, hopefully the last time for this batch.	Gabe Black
2012-01-31	clang: Enable compiling gem5 using clang 2.9 and 3.0	Koan-Sin Tan
2012-01-31	CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5	Geoffrey Blake
2012-01-30	Merge with main repository.	Gabe Black
2012-01-30	MEM: Clean-up of Functional/Virtual/TranslatingPort remnants	Andreas Hansson
2012-01-29	Yet another merge with the main repository.	Gabe Black
2012-01-29	Implement Ali's review feedback.	Gabe Black
2012-01-28	O3 CPU LSQ: Implement TSO	Nilay Vaish
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-16	Merge yet again with the main repository.	Gabe Black
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	CPU: Moving towards a more general port across CPU models	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson