index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
cpu
/
o3
Age
Commit message (
Expand
)
Author
2010-02-12
O3PCU: Split loads and stores that cross cache line boundaries.
Timothy M. Jones
2009-11-04
o3: get rid of unused physmem pointer
Steve Reinhardt
2009-09-26
O3: Add flag to control whether faulting instructions are traced.
Steve Reinhardt
2009-09-26
O3: Mark fetch stage as active if it faults.
Steve Reinhardt
2009-09-23
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
Nathan Binkert
2009-09-22
python: Move more code into m5.util allow SCons to use that code.
Nathan Binkert
2009-08-01
Fix setting of INST_FETCH flag for O3 CPU.
Steve Reinhardt
2009-07-25
o3-smt: enforce numThreads parameter for SMT SE mode
Korey Sewell
2009-07-08
Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
Gabe Black
2009-07-08
Registers: Add a registers.hh file as an ISA switched header.
Gabe Black
2009-07-08
Registers: Get rid of the float register width parameter.
Gabe Black
2009-07-08
Registers: Add an ISA object which replaces the MiscRegFile.
Gabe Black
2009-06-04
move: put predictor includes and cc files into the same place
Nathan Binkert
2009-05-26
types: add a type for thread IDs and try to use it everywhere
Nathan Binkert
2009-05-17
includes: sort includes again
Nathan Binkert
2009-05-17
types: Move stuff for global types into src/base/types.hh
Nathan Binkert
2009-05-12
inorder-o3: allow both to compile together
Korey Sewell
2009-05-12
inorder-bpred: edits to handle non-delay-slot ISAs
Korey Sewell
2009-04-19
Mem: Change isLlsc to isLLSC.
Gabe Black
2009-04-19
Memory: Rename LOCKED for load locked store conditional to LLSC.
Gabe Black
2009-04-18
o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ...
Korey Sewell
2009-04-17
o3, inorder: fix FS bug due to initializing ThreadState to Halted.
Steve Reinhardt
2009-04-15
o3: handle fetch with no active threads correctly.
Steve Reinhardt
2009-04-15
o3: fix {read,set}ArchFloatReg* functions.
Steve Reinhardt
2009-04-15
ThreadState: initialize status to Halted in constructor.
Steve Reinhardt
2009-04-15
Get rid of the Unallocated thread context state.
Steve Reinhardt
2009-04-08
tlb: More fixing of unified TLB
Nathan Binkert
2009-04-08
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
Gabe Black
2009-03-07
stats: fix duplicate statistics names.
Nathan Binkert
2009-03-05
stats: Fix all stats usages to deal with template fixes
Nathan Binkert
2009-03-04
O3: Make numThreads error message more helpful.
Steve Reinhardt
2009-02-27
Processes: Make getting and setting system call arguments part of a process o...
Gabe Black
2009-02-26
CPA: Add code to automatically record function symbols as CPU executes.
Ali Saidi
2009-02-25
ISA: Replace the translate functions in the TLBs with translateAtomic.
Gabe Black
2009-02-25
CPU: Get rid of translate... functions from various interface classes.
Gabe Black
2009-02-10
CPU: Prepare CPU models for the new in-order CPU model.
Korey Sewell
2009-01-24
cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep.
Nathan Binkert
2009-01-21
o3cpu: give a name to the activity recorder for better tracing
Nathan Binkert
2009-01-19
thread_context: move getSystemPtr so SE mode can get to it.
Nathan Binkert
2008-12-06
eventq: use the flags data structure
Nathan Binkert
2008-11-10
O3CPU: Make the instcount debugging stuff per-cpu.
Clint Smullen
2008-11-04
get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
Lisa Hsu
2008-11-02
Add in Context IDs to the simulator. From now on, cpuId is almost never used,
Lisa Hsu
2008-11-02
make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
Lisa Hsu
2008-10-23
s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in
Lisa Hsu
2008-10-21
style: Use the correct m5 style for things relating to interrupts.
Nathan Binkert
2008-10-20
O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo...
Ali Saidi
2008-10-12
Get rid of old RegContext code.
Gabe Black
2008-10-12
Turn Interrupts objects into SimObjects. Also, move local APIC state into x86...
Gabe Black
2008-10-11
CPU: Eliminate the simPalCheck funciton.
Gabe Black
[next]
