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Age
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Author
2013-02-15
sim: Add a system-global option to bypass caches
Andreas Sandberg
2013-02-15
cpu: Refactor memory system checks
Andreas Sandberg
2013-02-15
cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy
Andreas Sandberg
2013-02-15
cpu: Add CPU metadata om the Python classes
Andreas Sandberg
2013-02-15
cpu: include set in o3/commit_impl.
Ali Saidi
2013-02-15
cpu: fix case with o3 cpu blocking and unblocking decode in cycle
Ali Saidi
2013-02-15
cpu: Fix a livelock in the o3 cpu.
Ali Saidi
2013-01-24
branch predictor: move out of o3 and inorder cpus
Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-22
o3 cpu: fix zero reg problem
Andrea Pellegrini
2013-01-22
x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch
Nilay Vaish
2013-01-19
O3 IEW: Make incrWb and decrWb clearer
Joel Hestness
2013-01-12
x86: Changes to decoder, corrects 9376
Nilay Vaish
2013-01-07
cpu: Unify the serialization code for all of the CPU models
Andreas Sandberg
2013-01-07
cpu: Rewrite O3 draining to avoid stopping in microcode
Andreas Sandberg
2013-01-07
cpu: Fix broken thread context handover
Andreas Sandberg
2013-01-07
cpu: Fix O3 LSQ debug dumping constness and formatting
Andreas Sandberg
2013-01-07
cpu: Fix broken squashAfter implementation in O3 CPU
Andreas Sandberg
2013-01-07
o3 cpu: Remove unused variables
Andreas Sandberg
2013-01-07
cpu: Rename defer_registration->switched_out
Andreas Sandberg
2013-01-07
cpu: Correctly call parent on switchOut() and takeOverFrom()
Andreas Sandberg
2013-01-07
cpu: Unify SimpleCPU and O3 CPU serialization code
Andreas Sandberg
2013-01-07
cpu: Initialize the O3 pipeline from startup()
Andreas Sandberg
2013-01-07
cpu: Implement a flat register interface in thread contexts
Andreas Sandberg
2013-01-07
cpu: Check that the memory system is in the correct mode
Andreas Sandberg
2013-01-07
arch: Make the ISA class inherit from SimObject
Andreas Sandberg
2013-01-07
o3: Fix issue with LLSC ordering and speculation
Ali Saidi
2013-01-07
cpu: rename the misleading inSyscall to noSquashFromTC
Ali Saidi
2013-01-04
Decoder: Remove the thread context get/set from the decoder.
Gabe Black
2012-12-06
TournamentBP: Fix some bugs with table sizes and counters
Erik Tomusk
2012-12-06
o3 cpu: remove some unused buggy functions in the lsq
Nathanael Premillieu
2012-11-02
sim: Move the draining interface into a separate base class
Andreas Sandberg
2012-11-02
cpu: O3 add a header declaring the DerivO3CPU
Andreas Sandberg
2012-11-02
cpu: Add header files for checker CPUs
Andreas Sandberg
2012-11-02
sim: Include object header files in SWIG interfaces
Andreas Sandberg
2012-09-25
O3: Pack the comm structures a bit better to reduce their size.
Ali Saidi
2012-09-25
CPU: Add abandoned instructions to O3 Pipe Viewer
Djordje Kovacevic
2012-09-12
stats: remove duplicate instruction stats from the commit stage
Anthony Gutierrez
2012-09-07
O3: Get rid of incorrect assert in RAS.
Ali Saidi
2012-09-07
Param: Transition to Cycles for relevant parameters
Andreas Hansson
2012-08-28
Clock: Add a Cycles wrapper class and use where applicable
Andreas Hansson
2012-08-28
Clock: Rework clocks to avoid tick-to-cycle transformations
Andreas Hansson
2012-08-22
Packet: Remove NACKs from packet and its use in endpoints
Andreas Hansson
2012-08-21
CPU: Remove overloaded function_trace_start parameter
Andreas Hansson
2012-08-21
Clock: Make Tick unsigned and remove UTick
Andreas Hansson
2012-08-15
O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...
Anthony Gutierrez
2012-07-27
checker: make checker cpu id match its host's cpu id
Anthony Gutierrez
2012-07-09
Port: Align port names in C++ and Python
Andreas Hansson
2012-07-09
Fix: Address a few benign memory leaks
Andreas Hansson
2012-06-29
O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.
Nathanael Premillieu
2012-06-05
ISA: Back-out NoopMachInst as a StaticInstPtr change.
Ali Saidi
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