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path: root/src/cpu/o3
AgeCommit message (Expand)Author
2011-04-15includes: fix up code after sortingNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-04-04ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.Ali Saidi
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-04-04CPU: Remove references to memory copy operationsAli Saidi
2011-04-04O3: Tighten memory order violation checking to 16 bytes.Ali Saidi
2011-03-17O3: Send instruction back to fetch on squash to seed predecoder correctly.Ali Saidi
2011-03-17O3: Cleanup the commitInfo comm struct.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-03-17O3: Fix unaligned stores when cache blockedAli Saidi
2011-02-25O3CPU: Fix iqCount and lsqCount SMT fetch policies.Timothy M. Jones
2011-02-23O3: When a prefetch causes a fault, don't record it in the instAli Saidi
2011-02-23O3: If there is an outstanding table walk don't let the inst queue sleep.Ali Saidi
2011-02-23ARM: Do something for ISB, DSB, DMBAli Saidi
2011-02-23ARM: Fix bug that let two table walks occur in parallel.Ali Saidi
2011-02-23O3: Fix bug when a squash occurs right before TLB miss returns.Ali Saidi
2011-02-13O3: Fetch from the microcode ROM when needed.Gabe Black
2011-02-13O3: Fix GCC 4.2.4 complaintAli Saidi
2011-02-11O3: Fix pipeline restart when a table walk completes in the fetch stage.Giacomo Gabrielli
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2011-02-06mcpat: Adds McPAT performance countersJoel Hestness
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2011-02-02O3: Fix a style bug in O3.Gabe Black
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black
2011-01-18O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.Matt Horsnell
2011-01-18O3: Don't test misprediction on load instructions until executed.Matt Horsnell
2011-01-18O3: Keep around the last committed instruction and use for squashing.Ali Saidi
2011-01-18O3: Don't try to scoreboard misc registers.Ali Saidi
2011-01-18O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.Matt Horsnell
2011-01-18O3: Fix mispredicts from non control instructions.Matt Horsnell
2011-01-18O3: Fixes the way prefetches are handled inside the iew unit.Matt Horsnell
2011-01-18O3: Support timing translations for O3 CPU fetch.Ali Saidi
2011-01-18ARM: Add support for moving predicated false dest operands from sources.Ali Saidi
2011-01-18O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.Min Kyu Jeong
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2011-01-03Move sched_list.hh and timebuf.hh from src/base to src/cpu.Steve Reinhardt
2010-12-07O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).Ali Saidi
2010-12-07O3: Support squashing all state after special instructionAli Saidi
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-11-18O3: Fix fp destination register flattening, and index offset adjusting.Gabe Black
2010-11-15O3: Make O3 support variably lengthed instructions.Gabe Black
2010-11-15O3: reset architetural state by calling clear()Ali Saidi
2010-11-15CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.Giacomo Gabrielli
2010-11-15O3: prevent a squash when completeAcc() modifies misc reg through TC.Min Kyu Jeong
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
2010-10-24O3: Get rid of a bunch of commented out lines.Gabe Black
2010-10-04Alpha: Fix Alpha NumMiscArchRegs constant.Gabe Black
2010-09-20CPU: Fix O3 and possible InOrder segfaults in FS.Gabe Black
2010-09-13CPU: Get rid of the now unnecessary getInst/setInst family of functions.Gabe Black