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path: root/src/cpu/o3
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2007-08-26Merge with headGabe Black
--HG-- extra : convert_revision : cc73b9aaf73e9dacf52f3350fa591e67ca4ccee6
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
--HG-- extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
2007-08-21Merge with head.Gabe Black
--HG-- extra : convert_revision : 9ef81afcfabd86c9c069204998c987344f03f33e
2007-08-21o3: Fix for retry ID bug.Kevin Lim
It should be cleared prior to the call to recvRetry. Add extra DPRINTF statement for clearer debugging output. --HG-- extra : convert_revision : e2332754743f42d60e159ac89f6fb0fd8b7f57f8
2007-08-13O3: Set up the predicted npc and nnpc for a fault carrying noop so that it ↵Gabe Black
doesn't cause a false branch mispredict. --HG-- extra : convert_revision : 2820597cc966cd7b128cef0dab48fe05089533d7
2007-08-13Move the "translate" member functions back into the base o3 class.Gabe Black
--HG-- extra : convert_revision : 3c480537bf38f74f0f1d72e75c70aa46ba91b759
2007-07-31Merge from head.Steve Reinhardt
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2007-07-30Fix problem with tracer not being initialized.Gabe Black
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2007-07-29Merge Gabe's changes from head.Steve Reinhardt
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2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
These need to be refined a little still and given parameters. --HG-- extra : convert_revision : 9a8f5a7bd9dacbebbbd2c235cd890c49a81040d7
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
--HG-- extra : convert_revision : e06a950964286604274fba81dcca362d75847233
2007-07-26X86: Fix argument register indexing.Gabe Black
Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg. --HG-- extra : convert_revision : f448a3ca4d6adc3fc3323562870f70eec05a8a1f
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-07-23Fix WriteReq/StoreCondReq setting in O3.Steve Reinhardt
--HG-- extra : convert_revision : b41571535f3d1f78df3cb6e48c16de5c7549d87f
2007-07-15Fix up a bunch of multilevel coherence issues.Steve Reinhardt
Atomic mode seems to work. Timing is closer but not there yet. --HG-- extra : convert_revision : 0dea5c3d4b973d009e9d4a4c21b9cad15961d56f
2007-06-30Make CPU models use new LoadLockedReq/StoreCondReq commands.Steve Reinhardt
--HG-- extra : convert_revision : ab78d9d1d88c3698edfd653d71c8882e1272b781
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
(they function as adjectives not nouns) --HG-- extra : convert_revision : 6506474ff3356ae8c80ed276c3608d8a4680bfdb
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
now encoded in cmd field. --HG-- extra : convert_revision : d67819b7e3ee4b9a5bf08541104de0a89485e90b
2007-06-28o3cpu build for mipsKorey Sewell
--HG-- extra : convert_revision : 2c0be7a8c0a54ba5b1b2b69468f788d20abc8452
2007-06-21Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro src/cpu/o3/fetch_impl.hh: hand merge --HG-- extra : convert_revision : 3f71f3ac2035eec8b6f7bceb6906edb4dd09c045
2007-06-20Fix compiler errors.Gabe Black
--HG-- extra : convert_revision : 2b10076a24cb36cb748e299011ae691f09c158cd
2007-06-20Don't do checker stuff if the checker is not definedNathan Binkert
--HG-- extra : convert_revision : 1c920b050c21e592a386410e4e9f45354f8e4441
2007-06-20Make sure all parameters have default values if they'reNathan Binkert
supposed to and make sure parameters have the right type. Also make sure that any object that should be an intermediate type has the right options set. --HG-- extra : convert_revision : d56910628d9a067699827adbc0a26ab629d11e93
2007-06-19Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into doughnut.hpl.hp.com:/home/gblack/newmem-o3-micro src/cpu/base_dyn_inst_impl.hh: src/cpu/o3/fetch_impl.hh: Hand merge --HG-- extra : convert_revision : 0c0692033ac30133672d8dfe1f1a27e9d9e95a3d
2007-06-19Make branches work by repopulating the predecoder every time through. This ↵Gabe Black
is probably fine as far as the predecoder goes, but the simple cpu might want to not refetch something it already has. That reintroduces the self modifying code problem though. --HG-- extra : convert_revision : 802197e65f8dc1ad657c6b346091e03cb563b0c0
2007-06-13Seperate the pc-pc and the pc of the incoming bytes, and get rid of the ↵Gabe Black
"moreBytes" which just takes a MachInst. src/arch/x86/predecoder.cc: Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. Also make the "opSize" field describe the number of bytes and not the log of the number of bytes. --HG-- extra : convert_revision : 3a5ec7053ec69c5cba738a475d8b7fd9e6e6ccc0
2007-06-09Use the right typeNathan Binkert
--HG-- extra : convert_revision : b5ca3153ca786ea4e86bfe83f7760ba9ee41a882
2007-06-01Fix typo so m5.fast will compileNathan Binkert
--HG-- extra : convert_revision : 8ceb816c17108d7cb65cb46d8dc2bd2753b0e0f0
2007-06-01don't generate trace data unless tracing is onAli Saidi
--HG-- extra : convert_revision : 3953ace8d481d758d6e0d89183c0a7e7bebcf681
2007-05-30Fix cut-n-pasto to make the path correctNathan Binkert
--HG-- extra : convert_revision : a6194cc9c3b2eb83dc8480ed0417b2246f07b4bd
2007-05-27Move SimObject python files alongside the C++ and fixNathan Binkert
the SConscript files so that only the objects that are actually available in a given build are compiled in. Remove a bunch of files that aren't used anymore. --HG-- rename : src/python/m5/objects/AlphaTLB.py => src/arch/alpha/AlphaTLB.py rename : src/python/m5/objects/SparcTLB.py => src/arch/sparc/SparcTLB.py rename : src/python/m5/objects/BaseCPU.py => src/cpu/BaseCPU.py rename : src/python/m5/objects/FuncUnit.py => src/cpu/FuncUnit.py rename : src/python/m5/objects/IntrControl.py => src/cpu/IntrControl.py rename : src/python/m5/objects/MemTest.py => src/cpu/memtest/MemTest.py rename : src/python/m5/objects/FUPool.py => src/cpu/o3/FUPool.py rename : src/python/m5/objects/FuncUnitConfig.py => src/cpu/o3/FuncUnitConfig.py rename : src/python/m5/objects/O3CPU.py => src/cpu/o3/O3CPU.py rename : src/python/m5/objects/OzoneCPU.py => src/cpu/ozone/OzoneCPU.py rename : src/python/m5/objects/SimpleOzoneCPU.py => src/cpu/ozone/SimpleOzoneCPU.py rename : src/python/m5/objects/BadDevice.py => src/dev/BadDevice.py rename : src/python/m5/objects/Device.py => src/dev/Device.py rename : src/python/m5/objects/DiskImage.py => src/dev/DiskImage.py rename : src/python/m5/objects/Ethernet.py => src/dev/Ethernet.py rename : src/python/m5/objects/Ide.py => src/dev/Ide.py rename : src/python/m5/objects/Pci.py => src/dev/Pci.py rename : src/python/m5/objects/Platform.py => src/dev/Platform.py rename : src/python/m5/objects/SimConsole.py => src/dev/SimConsole.py rename : src/python/m5/objects/SimpleDisk.py => src/dev/SimpleDisk.py rename : src/python/m5/objects/Uart.py => src/dev/Uart.py rename : src/python/m5/objects/AlphaConsole.py => src/dev/alpha/AlphaConsole.py rename : src/python/m5/objects/Tsunami.py => src/dev/alpha/Tsunami.py rename : src/python/m5/objects/T1000.py => src/dev/sparc/T1000.py rename : src/python/m5/objects/Bridge.py => src/mem/Bridge.py rename : src/python/m5/objects/Bus.py => src/mem/Bus.py rename : src/python/m5/objects/MemObject.py => src/mem/MemObject.py rename : src/python/m5/objects/PhysicalMemory.py => src/mem/PhysicalMemory.py rename : src/python/m5/objects/BaseCache.py => src/mem/cache/BaseCache.py rename : src/python/m5/objects/CoherenceProtocol.py => src/mem/cache/coherence/CoherenceProtocol.py rename : src/python/m5/objects/Repl.py => src/mem/cache/tags/Repl.py rename : src/python/m5/objects/Process.py => src/sim/Process.py rename : src/python/m5/objects/Root.py => src/sim/Root.py rename : src/python/m5/objects/System.py => src/sim/System.py extra : convert_revision : 173f8764bafa8ef899198438fa5573874e407321
2007-05-21Change getDeviceAddressRanges to use bool for snoop arg.Steve Reinhardt
--HG-- extra : convert_revision : 832e52ba80cbab2f5bb6d5b5977a499d41b4d638
2007-05-12Make sure all addresses used in syscalls are truncated to 32 bits. Actually ↵Gabe Black
-all- arguements are truncated to 32 bits, but we should be able to get away with it. --HG-- extra : convert_revision : 3b8766c68a4ab36e2e769fac4812657f3f7e0d1c
2007-05-09Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into doughnut.mwconnections.com:/home/gblack/newmem-o3-micro --HG-- extra : convert_revision : 545b9e98eb1895f4b9e782224fb6615c71ed6323
2007-04-26Remove extra delete that was causing segfault.Kevin Lim
--HG-- extra : convert_revision : 8a27ed80308c95988f3bc43d670dc0ac9e946d39
2007-04-26Remove unnecessary check.Kevin Lim
--HG-- extra : convert_revision : 8cc2943ebc41e4d430789ee7923dd0dc878be06b
2007-04-23Merge zizzer.eecs.umich.edu:/n/wexford/x/gblack/m5/newmem-o3-specGabe Black
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-o3-micro --HG-- extra : convert_revision : 757e1d79033e6f8e0aaaf5ecaf14077d416cff8e
2007-04-23Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemGabe Black
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem-o3-spec --HG-- extra : convert_revision : 12f10c174f0eca1ddf74b672414fbe78251f686b
2007-04-22Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head --HG-- extra : convert_revision : 05f738ab6cf1e8bd2940f4ce20602f1e8ad1af48
2007-04-22Use proper cycles for IPC and CPI equations.Kevin Lim
src/cpu/o3/cpu.cc: Use proper cycles for these equations. --HG-- extra : convert_revision : cd49410eed978c789d788e80462abed6cb89fbae
2007-04-22Make the floating point zero register special handling only apply for ALPHA.Gabe Black
--HG-- extra : convert_revision : 4f393a5471656b29cecbacfcb337992239775915
2007-04-21fixes for solaris compileAli Saidi
--HG-- extra : convert_revision : c82a62a61650e3700d237da917c453e5a9676320
2007-04-15Make an inner loop which pulls microops out of macroops. These aren't ↵Gabe Black
checked for control flow because we can pull out microops until we run out of buffer. This prevents microops from being interpretted as branches because the pc doesn't become npc. --HG-- extra : convert_revision : 9fff7c6c32900692bbc567ecb75701c9c73da259
2007-04-15Add extra constructors to Alpha and MIPSGabe Black
--HG-- extra : convert_revision : 26ea87bfe9e5c27134eb9a15bf9e4629afae6c69
2007-04-14Add support for microcode and pull out the special branch delay slot ↵Gabe Black
handling. Branch delay slots need to be squash on a mispredict as well because the nnpc they saw was incorrect. --HG-- extra : convert_revision : 8b9c603616bcad254417a7a3fa3edfb4c8728719
2007-04-13Remove most of the special handling for delay slots since they have to be ↵Gabe Black
squashed anyway on a mispredict. This is because the NNPC value they saw when executing was incorrect. --HG-- extra : convert_revision : b42c4eb28b4fbba66c65cbd0a5033bf886c1532d
2007-04-09Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/head --HG-- extra : convert_revision : a250eed999be9b8acd6f420fdfe8f1b02905beb1
2007-04-09Fix bug when blocking due to no free registers.Kevin Lim
--HG-- extra : convert_revision : a1a218d3294515184689041487057495223360b7
2007-04-08Take into account that the flattened integer register space is a different ↵Gabe Black
size than the architected one. Also fixed some asserts. --HG-- extra : convert_revision : 26e7863919d1b976ba8cad747af475a6f18e9440
2007-04-08Get the "hard" SPARC instructions working in o3. I don't like that the ↵Gabe Black
IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly. --HG-- extra : convert_revision : cfd32808592832d7b6fbdaace5ae7b17c8a246e9
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