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path: root/src/cpu/o3
AgeCommit message (Expand)Author
2011-08-19O3: Squash the violator and younger instructions instead not all insts.Giacomo Gabrielli
2011-08-16O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively.Gabe Black
2011-08-14O3: When squashing, restore the macroop that should be used for fetching.Gabe Black
2011-08-14O3: Add a pointer to the macroop for a microop in the dyninst.Gabe Black
2011-08-13O3: At the end of an instruction, force fetchAddr to something sensible.Gabe Black
2011-08-09O3: Stop using the current macroop no matter why you're leaving it.Gabe Black
2011-08-09O3: When waiting to handle an interrupt, let everything drain out.Gabe Black
2011-08-07O3: Get rid of the unused addToRemoveList function.Gabe Black
2011-08-07O3: Let squashed and deferred instructions issue.Gabe Black
2011-08-02O3: Get rid of the raw ExtMachInst constructor on DynInsts.Gabe Black
2011-07-31O3: Implement memory mapped IPRs for O3.Gabe Black
2011-07-30O3: Fix corner case squashing into the microcode ROM.Gabe Black
2011-07-15O3: Create a pipeline activity viewer for the O3 CPU model.Giacomo Gabrielli
2011-07-10O3: Fix up pipelining icache accesses in fetch stage to function properlyGeoffrey Blake
2011-07-10O3: Make sure fetch doesn't go off into the weeds during speculation.Ali Saidi
2011-06-10o3: missing newlines on some dprintfsKorey Sewell
2011-06-02scons: rename TraceFlags to DebugFlagsNathan Binkert
2011-05-23O3: Fix offset calculation into storeQueue buffer for store->load forwardingGeoffrey Blake
2011-05-23O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.Geoffrey Blake
2011-05-23O3: Fix issue with interrupts/faults occuring in the middle of a macro-opGeoffrey Blake
2011-05-13O3: Fix an issue with a load & branch instruction and mem dep squashingGeoffrey Blake
2011-05-04O3: Remove assertion for case that is actually handled in code.Ali Saidi
2011-05-04O3: Fix a small corner case with the lsq hazard detection logic.Ali Saidi
2011-04-20stats: one more name violationNathan Binkert
2011-04-19stats: rename stats so they can be used as python expressionsNathan Binkert
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: fix up code after sortingNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-04-04ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.Ali Saidi
2011-04-04ARM: Cleanup implementation of ITSTATE and put important code in PCState.Ali Saidi
2011-04-04CPU: Remove references to memory copy operationsAli Saidi
2011-04-04O3: Tighten memory order violation checking to 16 bytes.Ali Saidi
2011-03-17O3: Send instruction back to fetch on squash to seed predecoder correctly.Ali Saidi
2011-03-17O3: Cleanup the commitInfo comm struct.Ali Saidi
2011-03-17Mem: Fix issue with dirty block being lost when entire block transferred to n...Ali Saidi
2011-03-17O3: Fix unaligned stores when cache blockedAli Saidi
2011-02-25O3CPU: Fix iqCount and lsqCount SMT fetch policies.Timothy M. Jones
2011-02-23O3: When a prefetch causes a fault, don't record it in the instAli Saidi
2011-02-23O3: If there is an outstanding table walk don't let the inst queue sleep.Ali Saidi
2011-02-23ARM: Do something for ISB, DSB, DMBAli Saidi
2011-02-23ARM: Fix bug that let two table walks occur in parallel.Ali Saidi
2011-02-23O3: Fix bug when a squash occurs right before TLB miss returns.Ali Saidi
2011-02-13O3: Fetch from the microcode ROM when needed.Gabe Black
2011-02-13O3: Fix GCC 4.2.4 complaintAli Saidi
2011-02-11O3: Fix pipeline restart when a table walk completes in the fetch stage.Giacomo Gabrielli
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2011-02-06mcpat: Adds McPAT performance countersJoel Hestness
2011-02-03Config: Keep track of uncached and cached ports separately.Gabe Black
2011-02-02O3: Fix a style bug in O3.Gabe Black
2011-02-01X86: Add L1 caches for the TLB walkers.Gabe Black