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path: root/src/cpu/o3
AgeCommit message (Expand)Author
2014-05-13mem: Refactor assignment of Packet typesCurtis Dunham
2014-09-03cpu: Fix o3 drain bugMitch Hayenga
2014-04-29arm: use condition code registers for ARM ISACurtis Dunham
2014-09-03cpu: Fix cache blocked load behavior in o3 cpuMitch Hayenga
2014-09-03cpu: Fix o3 quiesce fetch bugMitch Hayenga
2014-09-03cpu: Fix SMT scheduling issue with the O3 cpuMitch Hayenga
2014-09-03cpu: Add a fetch queue to the o3 cpuMitch Hayenga
2014-09-03cpu: Fix o3 front-end pipeline interlock behaviorMitch Hayenga
2014-09-03cpu: Change writeback modeling for outstanding instructionsMitch Hayenga
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-06-30cpu: implement a bi-mode branch predictorAnthony Gutierrez
2014-06-21o3: make dispatch LSQ full check more selectiveBinh Pham
2014-06-21o3: split load & store queue full cases in renameBinh Pham
2014-05-31style: eliminate equality tests with true and falseSteve Reinhardt
2014-05-23cpu: o3: remove stat totalCommittedInstsNilay Vaish
2014-05-09cpu: add more instruction mix statisticsCurtis Dunham
2014-05-09cpu, arm: Allow the specification of a socket fieldAkash Bagdia
2014-04-01cpu: Fix case where o3 lsq could print out uninitialized dataMitch Hayenga
2014-04-23cpu: Add O3 CPU width checksDam Sunwoo
2014-04-19o3: Fix occupancy checks for SMTFaissal Sleiman
2014-03-25cpu: o3: lsq: Fix TSO implementationMarco Elver
2014-03-12alpha: Small removal of dead comments/code from alpha ISAPaul Rosenfeld
2014-03-07cpu: Make CPU and ThreadContext getters constAndreas Hansson
2014-03-07scons: Fixes uninitialized warnings issued by clangMitch Hayenga
2014-01-24checker: CheckerCPU handling of MiscRegs was incorrectGeoffrey Blake
2014-01-24arch, cpu: Add support for flattening misc register indexes.Ali Saidi
2014-01-24cpu: Add support for Memory+Barrier instruction types in O3 cpu.Giacomo Gabrielli
2014-01-24cpu: Add support for instructions that zero cache lines.Ali Saidi
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2014-01-24base: add support for probe points and common probesMatt Horsnell
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
2014-01-24cpu: Relax check on squashed non-speculative instructionsAndreas Hansson
2013-12-03cpu: call BaseCPU startup() function in o3 cpuNilay Vaish
2013-11-15cpu: allow the fetch buffer to be smaller than a cache lineAnthony Gutierrez
2013-10-31cpu: Construct ROB with cpu params struct instead of each variableFaissal Sleiman
2013-10-31cpu: Fix O3 issuse with load+barrier instructions.Ali Saidi
2013-10-17cpu: add consistent guarding to *_impl.hh files.Matt Horsnell
2013-10-17cpu: Removing an unused variable in renameFaissal Sleiman
2013-10-17cpu: Change IEW DPRINTF to use IEW debug flagFaissal Sleiman
2013-10-17cpu: Put in assertions to check for maximum supported LQ/SQ sizeFaissal Sleiman
2013-10-15arch/x86: add support for explicit CC register fileYasuko Eckert
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-10-15cpu/o3: clean up rename map and free listSteve Reinhardt
2013-10-15cpu: rename *_DepTag constants to *_Reg_BaseSteve Reinhardt
2013-10-15cpu/o3: clean up scoreboard objectSteve Reinhardt
2013-10-15cpu/o3: clean up physical register fileSteve Reinhardt
2013-10-15cpu: clean up architectural register classificationSteve Reinhardt
2013-09-11cpu: Dynamically instantiate O3 CPU LSQUnitsJoel Hestness
2013-09-04cpu: Move the branch predictor out of the BaseCPUAndreas Hansson
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