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extra : convert_revision : 7f082ba5c1cd2445aec731950c31a877aac23a75
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extra : convert_revision : 717b62510f28a69af99453309fbbb458359eeb2a
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extra : convert_revision : 40dfbb72c4e418c54e909c54dad5fe6ef7017cb4
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extra : convert_revision : 746bdf92334d220158eb0eb6bf113b4dcedbb354
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src/cpu/o3/fetch_impl.hh:
Fetch needs to make sure it isn't waiting on an Icache access.
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extra : convert_revision : b53eb58b9e5a00bdb394134586d1f84f84d1c6e1
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : b98236507bb8996ce605b48b5a5a6a7aac297dc5
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extra : convert_revision : 661b412b0ae670181b89cb7dbc5e9d813804aa7a
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src/arch/alpha/interrupts.hh:
No need for this now that the ThreadContext is being used to set these IPRs in interrupts.
Also split up the interrupt checking from the updating of the IPL and interrupt summary.
src/arch/alpha/tlb.cc:
Check the PC for whether or not it's in PAL mode, not the addr.
src/cpu/o3/alpha/cpu.hh:
Split up getting the interrupt from actually processing the interrupt.
src/cpu/o3/alpha/cpu_impl.hh:
Splut up the processing of interrupts.
src/cpu/o3/commit_impl.hh:
Update for ISA-oriented interrupt changes.
src/cpu/o3/fetch_impl.hh:
Fix broken if statement from PcPAL updates, and properly populate the request fields.
Also more debugging output.
src/cpu/ozone/cpu_impl.hh:
Updates for ISA-oriented interrupt stuff.
src/cpu/ozone/front_end_impl.hh:
Populate request fields properly.
src/cpu/simple/base.cc:
Update for interrupt stuff.
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extra : convert_revision : 9bac3f9ffed4948ee788699b2fa8419bc1ca647c
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the parameters to the BaseCPU object.
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extra : convert_revision : 557292cffb40918133647b0c9ac653ee5112df2e
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impression that this code is ISA independent.
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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extra : convert_revision : 0c2db1e1b5fdb91c1ac5705ab872a6bfb575a67a
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extra : convert_revision : b3e9fa094d68f608865dedfc9f3f4125a20fd748
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : dafe2d4a032b277c219ea13faf20567c20c1f2f4
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src/cpu/o3/cpu.cc:
Handle draining properly when CPU isn't actually being used.
src/cpu/simple/atomic.cc:
Be sure to set status properly when draining.
src/mem/bus.cc:
Fix for draining.
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extra : convert_revision : d9796e6693e974f022159029fc9743c49a970c8f
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : dc165840841bdd88e40111b98d1be493441703f0
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extra : convert_revision : b5b7cdf4a5e5e54228c592093516bf18d0f7dbe6
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rename : src/kern/alpha/idle_event.cc => src/arch/alpha/idle_event.cc
rename : src/kern/alpha/idle_event.hh => src/arch/alpha/idle_event.hh
rename : src/kern/alpha/kernel_stats.cc => src/arch/alpha/kernel_stats.cc
rename : src/kern/alpha/kernel_stats.hh => src/arch/alpha/kernel_stats.hh
rename : src/kern/sparc/kernel_stats.hh => src/arch/sparc/kernel_stats.hh
rename : src/kern/base_kernel_stats.cc => src/kern/kernel_stats.cc
rename : src/kern/base_kernel_stats.hh => src/kern/kernel_stats.hh
extra : convert_revision : 42bd3e36b407edbd19b912c9218f4e5923a15966
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src/cpu/o3/mem_dep_unit_impl.hh:
Initialize mem dep unit properly, add debug output.
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extra : convert_revision : 3c56dedfa57de1edc4b1c8f8d9bc94e18002eff2
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extra : convert_revision : 7b58f75e5efc3c9ead2434f87605cbabcb23d90a
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base kernel_stats to base_kernel_stats
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extra : convert_revision : 2a010d2eb7ea2586ff063b99b8bcde6eb1e8e017
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
src/SConscript:
SCCS merged
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extra : convert_revision : f130c8a2d33f58d857e5d5a02bb9698c1bceb23b
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but isn't tested. Other architectures will not.
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extra : convert_revision : fc7e1e73e2f3b1a4ab9905a1eb98c5f07c6c8707
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src/cpu/o3/lsq_unit_impl.hh:
Be sure to initialize pointer to NULL.
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extra : convert_revision : 917d5119e4bd8eae10959ed07069d8c694315c7a
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are in PAL mode, however.
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extra : convert_revision : b52d9642efc474eaf97437fa2df879efefa0062b
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records when interrupts are requested, and returns an interrupt to execute if the
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extra : convert_revision : c535000a6a170caefd441687b60f940513d29739
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into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem-busfix
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extra : convert_revision : a9a41e2c292bd95aa148e1cf4d9a77c0622a462b
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src/arch/alpha/utility.hh:
For now makeExtMI will be specific to the ISA.
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extra : convert_revision : 89959c6499efcc3df9301ad8ea039580764a1496
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into zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops
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extra : convert_revision : c2f7398a0d14dd11108579bb243ada7420285a22
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file functions to not take faults
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extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
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for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
No need for mem parameter any more.
src/cpu/checker/cpu.cc:
Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
Remove memory parameter.
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extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
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extra : convert_revision : 581f97dafc2b30bd5067f6ff7f9cdbabc6890622
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functions.
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extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
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extra : convert_revision : 161c35ade82f2471e605d948dca56cfa216693fd
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change warning to a DPRINTF.
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extra : convert_revision : 819bade049d7ffd97d316051c99146ece5e3a651
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src/cpu/base_dyn_inst.hh:
Extend BaseDynInst a little bit so it can be use as a TC as well (specifically for ll/sc code).
src/cpu/base_dyn_inst_impl.hh:
Add variable to track if the result of the instruction should be recorded.
src/cpu/o3/alpha/cpu_impl.hh:
Clear lock flag upon hwrei.
src/cpu/o3/lsq_unit.hh:
Use ISA specified handling of locked reads.
src/cpu/o3/lsq_unit_impl.hh:
Use ISA specified handling of locked writes.
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extra : convert_revision : 1f5c789c35deb4b016573c02af4aab60d726c0e5
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
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extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
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and call it packet_access.hh and fix the #includes so
things compile right.
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extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
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?? doesn't compile in warn statements
Should have been false, where I had a true.
src/cpu/o3/lsq_impl.hh:
Apparently you can't have ?? in a warn statement (Something about trigraphs)
src/mem/cache/cache_impl.hh:
Forgot to signal atomic mode in snoopProbe
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extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426
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into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
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extra : convert_revision : c6611b32537918f5bf183788227ddf69a9a9a069
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--HG--
extra : convert_revision : 0cd0d31db44fe7e8e44bde90e1756873faca422f
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Still a bug in atomic uni-coherence in FS.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
Only deallocate once
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extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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extra : convert_revision : 898976bbd322e55bc234035456df8090c6dcf72d
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but I believe it should fix what she's running into (which was definitely a bug).
src/cpu/o3/fetch_impl.hh:
Move assertion to area where it should really always be true. Sometimes you might recvRetry and not necessarily be blocked (if there was a squash).
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extra : convert_revision : 76ad35357e7f4c44fa544ffed071096a62053018
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
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extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a
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into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
Hand merge.
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extra : convert_revision : a58cc439eb5e8f900d175ed8b5a85b6c8723e558
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src/cpu/o3/cpu.cc:
Comment out reseting CPU structures for now. This can be updated to work in the future.
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extra : convert_revision : bc1a86e2fe47da5acb14ba8b64568b0355431f1c
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src/cpu/o3/lsq_unit.hh:
Be sure to delete data if the cache is blocked.
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extra : convert_revision : fafbcfb8937e85555823942e69e798e557a600e5
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src/cpu/o3/cpu.cc:
Fix up caches plus sampling switch over.
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extra : convert_revision : 49d0c16d4c5e8d5ba83749d568a4efe3b42e3a97
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src/cpu/o3/cpu.cc:
Extra debugging, fix a bug brought up on bug tracker.
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extra : convert_revision : 23f8b166ba0d0af54e15b651ed28f59a1bc9d2f2
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