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path: root/src/cpu/o3
AgeCommit message (Expand)Author
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-12-21cpu: Resolve targets of predicted 'taken' decode for O3Arthur Perais
2016-12-21cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3Arthur Perais
2016-10-15cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClassFernando Endo
2016-09-22cpu: Fix the O3 CPU DrainRekai Gonzalez-Alberquilla
2016-09-13sim: Refactor quiesce and remove FS assertsMichael LeBeane
2016-06-06pwr: Low-power idle power state for idle CPUsDavid Guillen Fandos
2016-06-06stats: Fixing regStats function for some SimObjectsDavid Guillen Fandos
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
2014-12-09power: Low-power idle power state for idle CPUsAkash Bagdia
2015-05-05cpu: Change literal integer constants to meaningful labelsRekai Gonzalez Alberquilla
2015-11-27base: Add support for changing output directoriesAndreas Sandberg
2015-08-10mem, cpu: Add assertions to snoop invalidation logicStephan Diestelhorst
2015-07-19cpu: Fix LLSC atomic CPU wakeupKrishnendra Nathella
2016-02-10mem: Deduce if cache should forward snoopsAndreas Hansson
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2016-02-06style: remove trailing whitespaceSteve Reinhardt
2016-01-17cpu: remove unnecessary data ptr from O3 internal read() funcsSteve Reinhardt
2015-12-31mem: Make cache terminology easier to understandAndreas Hansson
2015-12-07cpu: Support virtual addr in elastic tracesRadhika Jagtap
2015-12-07cpu: Create record type enum for elastic tracesRadhika Jagtap
2015-12-07proto, probe: Add elastic trace probe to o3 cpuRadhika Jagtap
2015-12-07probe: Add probe in Fetch, IEW, Rename and CommitRadhika Jagtap
2015-12-04cpu: fix unitialized variable which may cause assertion failurePau Cabre
2015-11-22cpu: Fix base FP and CC register index in o3 insertThread()Nathanael Premillieu
2015-11-16o3: drop unused statistic wbPenalized and wbPenalizedRateNilay Vaish
2015-10-12misc: Add explicit overrides and fix other clang >= 3.5 issuesAndreas Hansson
2015-10-12misc: Remove redundant compiler-specific definesAndreas Hansson
2015-10-09isa: Add parameter to pick different decoder inside ISARekai Gonzalez Alberquilla
2015-09-30cpu,isa,mem: Add per-thread wakeup logicMitch Hayenga
2015-09-30isa,cpu: Add support for FS SMT InterruptsMitch Hayenga
2015-09-30cpu: Add per-thread monitorsMitch Hayenga
2015-09-15cpu, o3: consider split requests for LSQ checksnoop operationsHongil Yoon
2015-08-07base: Declare a type for context IDsAndreas Sandberg
2015-07-20cpu: Fixed a bug on where to fetch the next instruction fromDavid Hashe
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
2015-07-26cpu: o3: slight correction to identation in rename_impl.hhNilay Vaish
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-07-04o3: correct the number of cc registers in rename mapNilay Vaish
2015-05-15misc: Appease gcc 5.1Andreas Hansson
2015-05-05mem, cpu: Add a separate flag for strictly ordered memoryAndreas Sandberg
2015-05-05mem: Snoop into caches on uncacheable accessesAndreas Hansson
2015-05-05cpu: Work around gcc 4.9 issues with Num_OpClassesAndreas Hansson
2015-04-29cpu: o3: replace issueLatency with bool pipelinedNilay Vaish
2015-04-29cpu: o3: single cycle default div microop latency on x86Nilay Vaish