| Age | Commit message (Expand) | Author |
|---|
| 2014-12-02 | cpu, o3: Ignored invalidate causing same-address load reordering | Marco Elver |
| 2014-12-02 | cpu: Move packet deallocation to recvTimingResp in the O3 CPU | Stephan Diestelhorst |
| 2014-12-02 | mem: Assume all dynamic packet data is array allocated | Andreas Hansson |
| 2014-12-02 | mem: Add const getters for write packet data | Andreas Hansson |
| 2014-11-14 | arm: Fixes based on UBSan and static analysis | Andreas Hansson |
| 2014-11-06 | x86 isa: This patch attempts an implementation at mwait. | Marc Orr |
| 2014-10-29 | cpu: Add writeback modeling for drain functionality | Mitch Hayenga |
| 2014-10-29 | cpu: Add drain check functionality to IEW | Mitch Hayenga |
| 2014-10-20 | cpu: o3: corrects base FP and CC register index in removeThread() | Nilay Vaish |
| 2014-10-16 | arch: Use shared_ptr for all Faults | Andreas Hansson |
| 2014-10-16 | o3: Use shared_ptr for MemDepEntry | Andreas Hansson |
| 2014-10-16 | cpu: Probe points for basic PMU stats | Andreas Sandberg |
| 2014-10-11 | cpu: Fix o3 SMT IQCount bug | Andrew Lukefahr |
| 2014-10-09 | cpu: Remove Ozone CPU from the source tree | Mitch Hayenga |
| 2014-09-27 | arch: Use const StaticInstPtr references where possible | Andreas Hansson |
| 2014-09-20 | cpu: Remove unused deallocateContext calls | Mitch Hayenga |
| 2014-09-20 | alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate | Mitch Hayenga |
| 2014-09-20 | base: Clean up redundant string functions and use C++11 | Andreas Hansson |
| 2014-09-19 | arch: Pass faults by const reference where possible | Andreas Hansson |
| 2014-09-19 | cpu: Use a deque in o3 rename instruction queue | Andreas Hansson |
| 2014-09-09 | cpu: Only iterate over possible threads on the o3 cpu | Mitch Hayenga |
| 2014-05-13 | mem: Refactor assignment of Packet types | Curtis Dunham |
| 2014-09-03 | cpu: Fix o3 drain bug | Mitch Hayenga |
| 2014-04-29 | arm: use condition code registers for ARM ISA | Curtis Dunham |
| 2014-09-03 | cpu: Fix cache blocked load behavior in o3 cpu | Mitch Hayenga |
| 2014-09-03 | cpu: Fix o3 quiesce fetch bug | Mitch Hayenga |
| 2014-09-03 | cpu: Fix SMT scheduling issue with the O3 cpu | Mitch Hayenga |
| 2014-09-03 | cpu: Add a fetch queue to the o3 cpu | Mitch Hayenga |
| 2014-09-03 | cpu: Fix o3 front-end pipeline interlock behavior | Mitch Hayenga |
| 2014-09-03 | cpu: Change writeback modeling for outstanding instructions | Mitch Hayenga |
| 2014-09-03 | arch, cpu: Factor out the ExecContext into a proper base class | Andreas Sandberg |
| 2014-06-30 | cpu: implement a bi-mode branch predictor | Anthony Gutierrez |
| 2014-06-21 | o3: make dispatch LSQ full check more selective | Binh Pham |
| 2014-06-21 | o3: split load & store queue full cases in rename | Binh Pham |
| 2014-05-31 | style: eliminate equality tests with true and false | Steve Reinhardt |
| 2014-05-23 | cpu: o3: remove stat totalCommittedInsts | Nilay Vaish |
| 2014-05-09 | cpu: add more instruction mix statistics | Curtis Dunham |
| 2014-05-09 | cpu, arm: Allow the specification of a socket field | Akash Bagdia |
| 2014-04-01 | cpu: Fix case where o3 lsq could print out uninitialized data | Mitch Hayenga |
| 2014-04-23 | cpu: Add O3 CPU width checks | Dam Sunwoo |
| 2014-04-19 | o3: Fix occupancy checks for SMT | Faissal Sleiman |
| 2014-03-25 | cpu: o3: lsq: Fix TSO implementation | Marco Elver |
| 2014-03-12 | alpha: Small removal of dead comments/code from alpha ISA | Paul Rosenfeld |
| 2014-03-07 | cpu: Make CPU and ThreadContext getters const | Andreas Hansson |
| 2014-03-07 | scons: Fixes uninitialized warnings issued by clang | Mitch Hayenga |
| 2014-01-24 | checker: CheckerCPU handling of MiscRegs was incorrect | Geoffrey Blake |
| 2014-01-24 | arch, cpu: Add support for flattening misc register indexes. | Ali Saidi |
| 2014-01-24 | cpu: Add support for Memory+Barrier instruction types in O3 cpu. | Giacomo Gabrielli |
| 2014-01-24 | cpu: Add support for instructions that zero cache lines. | Ali Saidi |
| 2014-01-24 | cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo... | Ali Saidi |
