Age | Commit message (Expand) | Author |
2011-06-10 | o3: missing newlines on some dprintfs | Korey Sewell |
2011-06-02 | scons: rename TraceFlags to DebugFlags | Nathan Binkert |
2011-05-23 | O3: Fix offset calculation into storeQueue buffer for store->load forwarding | Geoffrey Blake |
2011-05-23 | O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache. | Geoffrey Blake |
2011-05-23 | O3: Fix issue with interrupts/faults occuring in the middle of a macro-op | Geoffrey Blake |
2011-05-13 | O3: Fix an issue with a load & branch instruction and mem dep squashing | Geoffrey Blake |
2011-05-04 | O3: Remove assertion for case that is actually handled in code. | Ali Saidi |
2011-05-04 | O3: Fix a small corner case with the lsq hazard detection logic. | Ali Saidi |
2011-04-20 | stats: one more name violation | Nathan Binkert |
2011-04-19 | stats: rename stats so they can be used as python expressions | Nathan Binkert |
2011-04-15 | trace: reimplement the DTRACE function so it doesn't use a vector | Nathan Binkert |
2011-04-15 | includes: fix up code after sorting | Nathan Binkert |
2011-04-15 | includes: sort all includes | Nathan Binkert |
2011-04-04 | ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works. | Ali Saidi |
2011-04-04 | ARM: Cleanup implementation of ITSTATE and put important code in PCState. | Ali Saidi |
2011-04-04 | CPU: Remove references to memory copy operations | Ali Saidi |
2011-04-04 | O3: Tighten memory order violation checking to 16 bytes. | Ali Saidi |
2011-03-17 | O3: Send instruction back to fetch on squash to seed predecoder correctly. | Ali Saidi |
2011-03-17 | O3: Cleanup the commitInfo comm struct. | Ali Saidi |
2011-03-17 | Mem: Fix issue with dirty block being lost when entire block transferred to n... | Ali Saidi |
2011-03-17 | O3: Fix unaligned stores when cache blocked | Ali Saidi |
2011-02-25 | O3CPU: Fix iqCount and lsqCount SMT fetch policies. | Timothy M. Jones |
2011-02-23 | O3: When a prefetch causes a fault, don't record it in the inst | Ali Saidi |
2011-02-23 | O3: If there is an outstanding table walk don't let the inst queue sleep. | Ali Saidi |
2011-02-23 | ARM: Do something for ISB, DSB, DMB | Ali Saidi |
2011-02-23 | ARM: Fix bug that let two table walks occur in parallel. | Ali Saidi |
2011-02-23 | O3: Fix bug when a squash occurs right before TLB miss returns. | Ali Saidi |
2011-02-13 | O3: Fetch from the microcode ROM when needed. | Gabe Black |
2011-02-13 | O3: Fix GCC 4.2.4 complaint | Ali Saidi |
2011-02-11 | O3: Fix pipeline restart when a table walk completes in the fetch stage. | Giacomo Gabrielli |
2011-02-11 | O3: Enhance data address translation by supporting hardware page table walkers. | Giacomo Gabrielli |
2011-02-06 | mcpat: Adds McPAT performance counters | Joel Hestness |
2011-02-03 | Config: Keep track of uncached and cached ports separately. | Gabe Black |
2011-02-02 | O3: Fix a style bug in O3. | Gabe Black |
2011-02-01 | X86: Add L1 caches for the TLB walkers. | Gabe Black |
2011-01-18 | O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA. | Matt Horsnell |
2011-01-18 | O3: Don't test misprediction on load instructions until executed. | Matt Horsnell |
2011-01-18 | O3: Keep around the last committed instruction and use for squashing. | Ali Saidi |
2011-01-18 | O3: Don't try to scoreboard misc registers. | Ali Saidi |
2011-01-18 | O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf. | Matt Horsnell |
2011-01-18 | O3: Fix mispredicts from non control instructions. | Matt Horsnell |
2011-01-18 | O3: Fixes the way prefetches are handled inside the iew unit. | Matt Horsnell |
2011-01-18 | O3: Support timing translations for O3 CPU fetch. | Ali Saidi |
2011-01-18 | ARM: Add support for moving predicated false dest operands from sources. | Ali Saidi |
2011-01-18 | O3: Fixes fetch deadlock when the interrupt clears before CPU handles it. | Min Kyu Jeong |
2011-01-07 | Replace curTick global variable with accessor functions. | Steve Reinhardt |
2011-01-03 | Move sched_list.hh and timebuf.hh from src/base to src/cpu. | Steve Reinhardt |
2010-12-07 | O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg). | Ali Saidi |
2010-12-07 | O3: Support squashing all state after special instruction | Ali Saidi |
2010-12-07 | O3: Make all instructions that write a misc. register not perform the write u... | Giacomo Gabrielli |