gem5 - gem5

Age	Commit message (Expand)	Author
2011-02-11	O3: Fix pipeline restart when a table walk completes in the fetch stage.	Giacomo Gabrielli
2011-02-11	O3: Enhance data address translation by supporting hardware page table walkers.	Giacomo Gabrielli
2011-02-06	mcpat: Adds McPAT performance counters	Joel Hestness
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2011-02-02	O3: Fix a style bug in O3.	Gabe Black
2011-02-01	X86: Add L1 caches for the TLB walkers.	Gabe Black
2011-01-18	O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.	Matt Horsnell
2011-01-18	O3: Don't test misprediction on load instructions until executed.	Matt Horsnell
2011-01-18	O3: Keep around the last committed instruction and use for squashing.	Ali Saidi
2011-01-18	O3: Don't try to scoreboard misc registers.	Ali Saidi
2011-01-18	O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.	Matt Horsnell
2011-01-18	O3: Fix mispredicts from non control instructions.	Matt Horsnell
2011-01-18	O3: Fixes the way prefetches are handled inside the iew unit.	Matt Horsnell
2011-01-18	O3: Support timing translations for O3 CPU fetch.	Ali Saidi
2011-01-18	ARM: Add support for moving predicated false dest operands from sources.	Ali Saidi
2011-01-18	O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.	Min Kyu Jeong
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2011-01-03	Move sched_list.hh and timebuf.hh from src/base to src/cpu.	Steve Reinhardt
2010-12-07	O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).	Ali Saidi
2010-12-07	O3: Support squashing all state after special instruction	Ali Saidi
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-12-07	O3: Support SWAP and predicated loads/store in ARM.	Min Kyu Jeong
2010-11-18	O3: Fix fp destination register flattening, and index offset adjusting.	Gabe Black
2010-11-15	O3: Make O3 support variably lengthed instructions.	Gabe Black
2010-11-15	O3: reset architetural state by calling clear()	Ali Saidi
2010-11-15	CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.	Giacomo Gabrielli
2010-11-15	O3: prevent a squash when completeAcc() modifies misc reg through TC.	Min Kyu Jeong
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black
2010-10-24	O3: Get rid of a bunch of commented out lines.	Gabe Black
2010-10-04	Alpha: Fix Alpha NumMiscArchRegs constant.	Gabe Black
2010-09-20	CPU: Fix O3 and possible InOrder segfaults in FS.	Gabe Black
2010-09-13	CPU: Get rid of the now unnecessary getInst/setInst family of functions.	Gabe Black
2010-09-13	Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.	Gabe Black
2010-09-10	style: fix sorting of includes and whitespace in some files	Nathan Binkert
2010-08-25	ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)	Min Kyu Jeong
2010-08-23	ISA: Get rid of old, unused utility functions cluttering up the ISAs.	Gabe Black
2010-08-23	O3: Skipping mem-order violation check for uncachable loads.	Min Kyu Jeong
2010-08-23	ARM: Improve printing of uop disassembly.	Min Kyu Jeong
2010-08-23	CPU: Make Exec trace to print predication result (if false) for memory instru...	Min Kyu Jeong
2010-08-23	ARM: mark msr/mrs instructions as SerializeBefore/After	Min Kyu Jeong
2010-08-23	O3: Handle loads when the destination is the PC.	Min Kyu Jeong
2010-08-23	ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.	Min Kyu Jeong
2010-08-13	CPU: Add readBytes and writeBytes functions to the exec contexts.	Gabe Black
2010-07-22	LSQ Unit: After deleting part of a split request, set it to NULL so that it	Timothy M. Jones
2010-07-22	O3CPU: Fix a bug where stores in the cpu where never marked as split.	Timothy M. Jones
2010-07-22	O3CPU: O3's tick event gets squashed when it is switched out. When repeatedly	Timothy M. Jones
2010-06-23	O3ThreadContext: When taking over from a previous context, only assert that	Timothy M. Jones
2010-02-26	cpu_models: get rid of cpu_models.py and move the stuff into SCons	Nathan Binkert
2010-02-12	O3PCU: Split loads and stores that cross cache line boundaries.	Timothy M. Jones
2009-11-04	o3: get rid of unused physmem pointer	Steve Reinhardt