gem5 - gem5

Age	Commit message (Expand)	Author
2014-10-09	cpu: Remove Ozone CPU from the source tree	Mitch Hayenga
2014-09-27	arch: Use const StaticInstPtr references where possible	Andreas Hansson
2014-09-20	cpu: Remove unused deallocateContext calls	Mitch Hayenga
2014-09-20	alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate	Mitch Hayenga
2014-09-20	base: Clean up redundant string functions and use C++11	Andreas Hansson
2014-09-19	arch: Pass faults by const reference where possible	Andreas Hansson
2014-09-19	cpu: Use a deque in o3 rename instruction queue	Andreas Hansson
2014-09-09	cpu: Only iterate over possible threads on the o3 cpu	Mitch Hayenga
2014-05-13	mem: Refactor assignment of Packet types	Curtis Dunham
2014-09-03	cpu: Fix o3 drain bug	Mitch Hayenga
2014-04-29	arm: use condition code registers for ARM ISA	Curtis Dunham
2014-09-03	cpu: Fix cache blocked load behavior in o3 cpu	Mitch Hayenga
2014-09-03	cpu: Fix o3 quiesce fetch bug	Mitch Hayenga
2014-09-03	cpu: Fix SMT scheduling issue with the O3 cpu	Mitch Hayenga
2014-09-03	cpu: Add a fetch queue to the o3 cpu	Mitch Hayenga
2014-09-03	cpu: Fix o3 front-end pipeline interlock behavior	Mitch Hayenga
2014-09-03	cpu: Change writeback modeling for outstanding instructions	Mitch Hayenga
2014-09-03	arch, cpu: Factor out the ExecContext into a proper base class	Andreas Sandberg
2014-06-30	cpu: implement a bi-mode branch predictor	Anthony Gutierrez
2014-06-21	o3: make dispatch LSQ full check more selective	Binh Pham
2014-06-21	o3: split load & store queue full cases in rename	Binh Pham
2014-05-31	style: eliminate equality tests with true and false	Steve Reinhardt
2014-05-23	cpu: o3: remove stat totalCommittedInsts	Nilay Vaish
2014-05-09	cpu: add more instruction mix statistics	Curtis Dunham
2014-05-09	cpu, arm: Allow the specification of a socket field	Akash Bagdia
2014-04-01	cpu: Fix case where o3 lsq could print out uninitialized data	Mitch Hayenga
2014-04-23	cpu: Add O3 CPU width checks	Dam Sunwoo
2014-04-19	o3: Fix occupancy checks for SMT	Faissal Sleiman
2014-03-25	cpu: o3: lsq: Fix TSO implementation	Marco Elver
2014-03-12	alpha: Small removal of dead comments/code from alpha ISA	Paul Rosenfeld
2014-03-07	cpu: Make CPU and ThreadContext getters const	Andreas Hansson
2014-03-07	scons: Fixes uninitialized warnings issued by clang	Mitch Hayenga
2014-01-24	checker: CheckerCPU handling of MiscRegs was incorrect	Geoffrey Blake
2014-01-24	arch, cpu: Add support for flattening misc register indexes.	Ali Saidi
2014-01-24	cpu: Add support for Memory+Barrier instruction types in O3 cpu.	Giacomo Gabrielli
2014-01-24	cpu: Add support for instructions that zero cache lines.	Ali Saidi
2014-01-24	cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...	Ali Saidi
2014-01-24	mem: per-thread cache occupancy and per-block ages	Dam Sunwoo
2014-01-24	base: add support for probe points and common probes	Matt Horsnell
2014-01-24	mem: track per-request latencies and access depths in the cache hierarchy	Matt Horsnell
2014-01-24	cpu: Relax check on squashed non-speculative instructions	Andreas Hansson
2013-12-03	cpu: call BaseCPU startup() function in o3 cpu	Nilay Vaish
2013-11-15	cpu: allow the fetch buffer to be smaller than a cache line	Anthony Gutierrez
2013-10-31	cpu: Construct ROB with cpu params struct instead of each variable	Faissal Sleiman
2013-10-31	cpu: Fix O3 issuse with load+barrier instructions.	Ali Saidi
2013-10-17	cpu: add consistent guarding to *_impl.hh files.	Matt Horsnell
2013-10-17	cpu: Removing an unused variable in rename	Faissal Sleiman
2013-10-17	cpu: Change IEW DPRINTF to use IEW debug flag	Faissal Sleiman
2013-10-17	cpu: Put in assertions to check for maximum supported LQ/SQ size	Faissal Sleiman
2013-10-15	arch/x86: add support for explicit CC register file	Yasuko Eckert