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path: root/src/cpu/o3
AgeCommit message (Expand)Author
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
2013-01-07cpu: Unify the serialization code for all of the CPU modelsAndreas Sandberg
2013-01-07cpu: Rewrite O3 draining to avoid stopping in microcodeAndreas Sandberg
2013-01-07cpu: Fix broken thread context handoverAndreas Sandberg
2013-01-07cpu: Fix O3 LSQ debug dumping constness and formattingAndreas Sandberg
2013-01-07cpu: Fix broken squashAfter implementation in O3 CPUAndreas Sandberg
2013-01-07o3 cpu: Remove unused variablesAndreas Sandberg
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07cpu: Correctly call parent on switchOut() and takeOverFrom()Andreas Sandberg
2013-01-07cpu: Unify SimpleCPU and O3 CPU serialization codeAndreas Sandberg
2013-01-07cpu: Initialize the O3 pipeline from startup()Andreas Sandberg
2013-01-07cpu: Implement a flat register interface in thread contextsAndreas Sandberg
2013-01-07cpu: Check that the memory system is in the correct modeAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-07o3: Fix issue with LLSC ordering and speculationAli Saidi
2013-01-07cpu: rename the misleading inSyscall to noSquashFromTCAli Saidi
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
2012-12-06TournamentBP: Fix some bugs with table sizes and countersErik Tomusk
2012-12-06o3 cpu: remove some unused buggy functions in the lsqNathanael Premillieu
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02cpu: O3 add a header declaring the DerivO3CPUAndreas Sandberg
2012-11-02cpu: Add header files for checker CPUsAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-09-25O3: Pack the comm structures a bit better to reduce their size.Ali Saidi
2012-09-25CPU: Add abandoned instructions to O3 Pipe ViewerDjordje Kovacevic
2012-09-12stats: remove duplicate instruction stats from the commit stageAnthony Gutierrez
2012-09-07O3: Get rid of incorrect assert in RAS.Ali Saidi
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-21CPU: Remove overloaded function_trace_start parameterAndreas Hansson
2012-08-21Clock: Make Tick unsigned and remove UTickAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-07-27checker: make checker cpu id match its host's cpu idAnthony Gutierrez
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Fix: Address a few benign memory leaksAndreas Hansson
2012-06-29O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.Nathanael Premillieu
2012-06-05ISA: Back-out NoopMachInst as a StaticInstPtr change.Ali Saidi
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-06-05sim: Remove FastAllocAli Saidi
2012-06-04ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.Gabe Black
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
2012-05-25Decode: Make the Decoder class defined per ISA.Gabe Black
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-30CPU: Unify initMemProxies across CPUs and simulation modesAndreas Hansson