Age | Commit message (Collapse) | Author |
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comments.
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Removing hwrei causes
the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal
call sys and thus the translation fails because the user is attempting to access a super page address.
Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think
this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs.
Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were
removed since a great deal of manual patching would be required to only remove the hwrei change.
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x86's Interrupts object.
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For now, there is still a single global event queue, but this is
necessary for making the steps towards a parallelized m5.
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--HG--
rename : src/cpu/o3/sparc/cpu_builder.cc => src/cpu/o3/cpu_builder.cc
rename : src/cpu/o3/sparc/dyn_inst.cc => src/cpu/o3/dyn_inst.cc
rename : src/cpu/o3/sparc/impl.hh => src/cpu/o3/impl.hh
rename : src/cpu/o3/sparc/thread_context.cc => src/cpu/o3/thread_context.cc
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--HG--
rename : src/cpu/o3/dyn_inst.hh => src/cpu/o3/dyn_inst_decl.hh
rename : src/cpu/o3/alpha/dyn_inst_impl.hh => src/cpu/o3/dyn_inst_impl.hh
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Even though we're not incorrect about operator precedence, let's add
some parens in some particularly confusing places to placate GCC 4.3
so that we don't have to turn the warning off. Agreed that this is a
bit of a pain for those users who get the order of operations correct,
but it is likely to prevent bugs in certain cases.
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Fix the logic in the LSQ that determines if there are any stores to
write back. In the commit stage, check for thread specific writebacks
instead of just any writeback.
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Just check CPU's nextPC before and after syscall and if it changes,
update this instruction's nextPC because the syscall must have changed
the nextPC.
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In the future, it would be nice to put the O3CPU into its own
namespace so that we don't end up hardcoding pointers to the global
namespace.
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should configure their editors to not insert tabs
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done to be consistent with its
python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused
problems for intialization of the interval value. If a child class's profile value was defined, the parent
BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the
multiple redifitions of profile in the child CPU classes.
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A whole bunch of stuff has been converted to use the new params stuff, but
the CPU wasn't one of them. While we're at it, make some things a bit
more stylish. Most of the work was done by Gabe, I just cleaned stuff up
a bit more at the end.
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a newly created one can.
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Force all non-default ports to provide a name and an
owner in the constructor.
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--HG--
extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
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This should help if somebody gets to the bug
fix before me (or someone else)...
--HG--
extra : convert_revision : 0ae64c58ef4f7b02996f31e9e9e6bfad344719e2
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you are squashing from the current instruction # causing the thread exit.
--HG--
extra : convert_revision : ccbeece7dd1d5fee43f30ab19370908972113473
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from the right point (#32 usually) instead of restarting at 0 and double-freeing.
Commented out assert line in free_list.hh that will check for when double-free condition
goes bad.
--HG--
extra : convert_revision : 08d5f9b6a874736e487d101e85c22aaa67bf59ae
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--HG--
extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
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--HG--
extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
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--HG--
extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af
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execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state.
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>
--HG--
extra : convert_revision : dafc16814383e8e8f8320845edf6ab2bcfed1e1d
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--HG--
extra : convert_revision : 73b753e57c355b7e6873f047ddc8cb371c3136b7
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--HG--
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--HG--
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--HG--
extra : convert_revision : 16fb8d7f3fbc5f8f1fc3ed34427c3d90a3125ad0
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"setShadowSet", "CacheOp"
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extra : convert_revision : a9ae8a7e62c27c2db16fd3cfa7a7f0bf5f0bf8ea
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--HG--
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--HG--
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--HG--
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This is necssary for fault handlers that branch to non-zero micro PCs.
--HG--
extra : convert_revision : c1cb4863d779a9f4a508d0b450e64fb7a985f264
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--HG--
extra : convert_revision : 4624ccd3f08818f4632881d6aca6d1cc343bbdcf
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file with them all.
--HG--
extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
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--HG--
extra : convert_revision : bc47206acb683ebaaa31f57af79b4b8db64e4d31
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--HG--
extra : convert_revision : 9dc4ea136c3c3f87a73d55e91bc4aae4eba70464
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parameters need to be fixed as well.
--HG--
extra : convert_revision : 0401970a79855ee0a96eb29305346ce07b5c98ea
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--HG--
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--HG--
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--HG--
extra : convert_revision : 940f92efd4a9dc59106e991cc6d9836861ab69de
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SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses
The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
--HG--
extra : convert_revision : d6faddde76e7c3361ebdbd0a7b372a40941c12ed
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--HG--
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--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
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