summaryrefslogtreecommitdiff
path: root/src/cpu/o3
AgeCommit message (Expand)Author
2015-07-26cpu: o3: slight correction to identation in rename_impl.hhNilay Vaish
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-07-07sim: Make the drain state a global typed enumAndreas Sandberg
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-07-04o3: correct the number of cc registers in rename mapNilay Vaish
2015-05-15misc: Appease gcc 5.1Andreas Hansson
2015-05-05mem, cpu: Add a separate flag for strictly ordered memoryAndreas Sandberg
2015-05-05mem: Snoop into caches on uncacheable accessesAndreas Hansson
2015-05-05cpu: Work around gcc 4.9 issues with Num_OpClassesAndreas Hansson
2015-04-29cpu: o3: replace issueLatency with bool pipelinedNilay Vaish
2015-04-29cpu: o3: single cycle default div microop latency on x86Nilay Vaish
2015-04-22cpu: remove conditional check (count > 0) on o3 IQ squashesBrandon Potter
2015-04-13cpu: re-organizes the branch predictor structure.Dibakar Gope
2015-04-03cpu: fix system total instructions accountingNikos Nikoleris
2015-03-09cpu: o3: another assert instead of checkNilay Vaish
2015-03-09cpu: o3: Remove unused code in iew, add assert instead.Nilay Vaish
2015-03-09cpu: o3: commit: mark pipeline delay variable as constsNilay Vaish
2015-03-09cpu: o3: remove unused stat variables.Nilay Vaish
2015-03-09cpu: o3: combine if with same conditionNilay Vaish
2015-03-09cpu: o3: remove member variable squashCounterNilay Vaish
2015-03-09cpu: o3: remove unused function annotateMemoryUnits()Nilay Vaish
2015-03-02cpu: o3 register renaming request handling improvedRekai
2015-03-02mem: Split port retry for all different packet classesAndreas Hansson
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2015-02-06cpu: Idle CPU status logic revisedAlexandru Dutu
2015-01-25cpu: Remove all notion that we know when the cpu is misspeculating.Ali Saidi
2014-12-05cpu: Only check for PC events on instruction boundaries.Gabe Black
2014-12-02cpu, o3: Ignored invalidate causing same-address load reorderingMarco Elver
2014-12-02cpu: Move packet deallocation to recvTimingResp in the O3 CPUStephan Diestelhorst
2014-12-02mem: Assume all dynamic packet data is array allocatedAndreas Hansson
2014-12-02mem: Add const getters for write packet dataAndreas Hansson
2014-11-14arm: Fixes based on UBSan and static analysisAndreas Hansson
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-10-29cpu: Add writeback modeling for drain functionalityMitch Hayenga
2014-10-29cpu: Add drain check functionality to IEWMitch Hayenga
2014-10-20cpu: o3: corrects base FP and CC register index in removeThread()Nilay Vaish
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
2014-10-16o3: Use shared_ptr for MemDepEntryAndreas Hansson
2014-10-16cpu: Probe points for basic PMU statsAndreas Sandberg
2014-10-11cpu: Fix o3 SMT IQCount bugAndrew Lukefahr
2014-10-09cpu: Remove Ozone CPU from the source treeMitch Hayenga
2014-09-27arch: Use const StaticInstPtr references where possibleAndreas Hansson
2014-09-20cpu: Remove unused deallocateContext callsMitch Hayenga
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-20base: Clean up redundant string functions and use C++11Andreas Hansson
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-09-19cpu: Use a deque in o3 rename instruction queueAndreas Hansson
2014-09-09cpu: Only iterate over possible threads on the o3 cpuMitch Hayenga
2014-05-13mem: Refactor assignment of Packet typesCurtis Dunham
2014-09-03cpu: Fix o3 drain bugMitch Hayenga
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-05 01:51:16 +0000