index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
cpu
/
o3
Age
Commit message (
Expand
)
Author
2013-10-15
cpu: rename *_DepTag constants to *_Reg_Base
Steve Reinhardt
2013-10-15
cpu/o3: clean up scoreboard object
Steve Reinhardt
2013-10-15
cpu/o3: clean up physical register file
Steve Reinhardt
2013-10-15
cpu: clean up architectural register classification
Steve Reinhardt
2013-09-11
cpu: Dynamically instantiate O3 CPU LSQUnits
Joel Hestness
2013-09-04
cpu: Move the branch predictor out of the BaseCPU
Andreas Hansson
2013-08-19
cpu: Fix a bug in the O3 CPU introduced by the cache line patch
Andreas Hansson
2013-07-18
mem: Set the cache line size on a system level
Andreas Hansson
2013-06-27
sim: Add the notion of clock domains to all ClockedObjects
Akash Bagdia
2013-06-27
cpu: Consider instructions waiting for FU completion in draining
Andreas Hansson
2013-04-22
sim: separate nextCycle() and clockEdge() in clockedObjects
Dam Sunwoo
2013-04-22
cpu: fix a switching issue with the o3 cpu.
Ali Saidi
2013-03-29
o3cpu: commit: changes interrupt handling
Nilay Vaish
2013-03-26
cpu: Remove CpuPort and use MasterPort in the CPU classes
Andreas Hansson
2013-03-04
cpu: fix a switching issue with the o3 cpu.
Ali Saidi
2013-02-19
scons: Fix up numerous warnings about name shadowing
Andreas Hansson
2013-02-15
cpu: Avoid duplicate entries in tracking structures for writes to misc regs
Geoffrey Blake
2013-02-15
cpu: Fix rename mis-handling serializing instructions when resource constrained
Geoffrey Blake
2013-02-15
o3: fix tick used for renaming and issue with range selection
Matt Horsnell
2013-02-15
sim: Add a system-global option to bypass caches
Andreas Sandberg
2013-02-15
cpu: Refactor memory system checks
Andreas Sandberg
2013-02-15
cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchy
Andreas Sandberg
2013-02-15
cpu: Add CPU metadata om the Python classes
Andreas Sandberg
2013-02-15
cpu: include set in o3/commit_impl.
Ali Saidi
2013-02-15
cpu: fix case with o3 cpu blocking and unblocking decode in cycle
Ali Saidi
2013-02-15
cpu: Fix a livelock in the o3 cpu.
Ali Saidi
2013-01-24
branch predictor: move out of o3 and inorder cpus
Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-22
o3 cpu: fix zero reg problem
Andrea Pellegrini
2013-01-22
x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch
Nilay Vaish
2013-01-19
O3 IEW: Make incrWb and decrWb clearer
Joel Hestness
2013-01-12
x86: Changes to decoder, corrects 9376
Nilay Vaish
2013-01-07
cpu: Unify the serialization code for all of the CPU models
Andreas Sandberg
2013-01-07
cpu: Rewrite O3 draining to avoid stopping in microcode
Andreas Sandberg
2013-01-07
cpu: Fix broken thread context handover
Andreas Sandberg
2013-01-07
cpu: Fix O3 LSQ debug dumping constness and formatting
Andreas Sandberg
2013-01-07
cpu: Fix broken squashAfter implementation in O3 CPU
Andreas Sandberg
2013-01-07
o3 cpu: Remove unused variables
Andreas Sandberg
2013-01-07
cpu: Rename defer_registration->switched_out
Andreas Sandberg
2013-01-07
cpu: Correctly call parent on switchOut() and takeOverFrom()
Andreas Sandberg
2013-01-07
cpu: Unify SimpleCPU and O3 CPU serialization code
Andreas Sandberg
2013-01-07
cpu: Initialize the O3 pipeline from startup()
Andreas Sandberg
2013-01-07
cpu: Implement a flat register interface in thread contexts
Andreas Sandberg
2013-01-07
cpu: Check that the memory system is in the correct mode
Andreas Sandberg
2013-01-07
arch: Make the ISA class inherit from SimObject
Andreas Sandberg
2013-01-07
o3: Fix issue with LLSC ordering and speculation
Ali Saidi
2013-01-07
cpu: rename the misleading inSyscall to noSquashFromTC
Ali Saidi
2013-01-04
Decoder: Remove the thread context get/set from the decoder.
Gabe Black
2012-12-06
TournamentBP: Fix some bugs with table sizes and counters
Erik Tomusk
2012-12-06
o3 cpu: remove some unused buggy functions in the lsq
Nathanael Premillieu
2012-11-02
sim: Move the draining interface into a separate base class
Andreas Sandberg
[next]