summaryrefslogtreecommitdiff
path: root/src/cpu/o3
AgeCommit message (Expand)Author
2012-09-25O3: Pack the comm structures a bit better to reduce their size.Ali Saidi
2012-09-25CPU: Add abandoned instructions to O3 Pipe ViewerDjordje Kovacevic
2012-09-12stats: remove duplicate instruction stats from the commit stageAnthony Gutierrez
2012-09-07O3: Get rid of incorrect assert in RAS.Ali Saidi
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-21CPU: Remove overloaded function_trace_start parameterAndreas Hansson
2012-08-21Clock: Make Tick unsigned and remove UTickAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-07-27checker: make checker cpu id match its host's cpu idAnthony Gutierrez
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
2012-07-09Fix: Address a few benign memory leaksAndreas Hansson
2012-06-29O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.Nathanael Premillieu
2012-06-05ISA: Back-out NoopMachInst as a StaticInstPtr change.Ali Saidi
2012-06-05O3: Clean up the O3 structures and try to pack them a bit better.Ali Saidi
2012-06-05sim: Remove FastAllocAli Saidi
2012-06-04ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.Gabe Black
2012-05-26CPU: Merge the predecoder and decoder.Gabe Black
2012-05-25Decode: Make the Decoder class defined per ISA.Gabe Black
2012-05-01MEM: Separate requests and responses for timing accessesAndreas Hansson
2012-04-14MEM: Remove the Broadcast destination from the packetAndreas Hansson
2012-04-14MEM: Separate snoops and normal memory requests/responsesAndreas Hansson
2012-04-06MEM: Enable multiple distributed generalized memoriesAndreas Hansson
2012-03-30MEM: Introduce the master/slave port sub-classes in C++William Wang
2012-03-30CPU: Unify initMemProxies across CPUs and simulation modesAndreas Hansson
2012-03-21O3: Fix sizing of decode to rename skid buffer.Andrew Lukefahr
2012-03-21O3: Fix size of skid buffer between fetch and decode when widths are differentBrian Grayson
2012-03-19gcc: Clean-up of non-C++0x compliant code, first stepsAndreas Hansson
2012-03-11O3: Add fatal when fetchWidth > Impl::MaxWidth.Brian Grayson
2012-03-09O3/Ozone: Eliminate dead code counting software prefetch instsGeoffrey Blake
2012-03-09CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectableGeoffrey Blake
2012-03-02CPU: Check that the interrupt controller is created when neededAndreas Hansson
2012-03-01x86: Fix switching of CPUsNilay Vaish
2012-02-24MEM: Make port proxies use references rather than pointersAndreas Hansson
2012-02-24CPU: Round-two unifying instr/data CPU ports across modelsAndreas Hansson
2012-02-13BPred: Fix RAS to handle predicated call/return instructions.Mrinmoy Ghosh
2012-02-13BP: Fix several Branch Predictor issues.Mrinmoy Ghosh
2012-02-12cpu: add separate stats for insts/ops both globally and per cpu modelAnthony Gutierrez
2012-02-12mem: Add a master ID to each request object.Ali Saidi
2012-02-10O3 CPU: Improve handling of delayed commit flagNilay Vaish
2012-02-10O3 CPU: Strengthen condition for handling interruptsNilay Vaish
2012-02-10O3 CPU: Provide the squashing instructionNilay Vaish
2012-02-10O3 Fetch: Check if PC is pointing to Microcode ROMNilay Vaish
2012-02-07Faults: Turn off arch/faults.hhGabe Black
2012-01-31Merge with head, hopefully the last time for this batch.Gabe Black
2012-01-31clang: Enable compiling gem5 using clang 2.9 and 3.0Koan-Sin Tan
2012-01-31CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5Geoffrey Blake
2012-01-30Merge with main repository.Gabe Black