| Age | Commit message (Expand) | Author |
|---|
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
| 2016-12-21 | cpu: Resolve targets of predicted 'taken' decode for O3 | Arthur Perais |
| 2016-12-21 | cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3 | Arthur Perais |
| 2016-10-15 | cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass | Fernando Endo |
| 2016-09-22 | cpu: Fix the O3 CPU Drain | Rekai Gonzalez-Alberquilla |
| 2016-09-13 | sim: Refactor quiesce and remove FS asserts | Michael LeBeane |
| 2016-06-06 | pwr: Low-power idle power state for idle CPUs | David Guillen Fandos |
| 2016-06-06 | stats: Fixing regStats function for some SimObjects | David Guillen Fandos |
| 2016-04-07 | mem: Remove threadId from memory request class | Mitch Hayenga |
| 2016-04-06 | Revert power patch sets with unexpected interactions | Andreas Sandberg |
| 2016-04-05 | mem: Remove threadId from memory request class | Mitch Hayenga |
| 2014-12-09 | power: Low-power idle power state for idle CPUs | Akash Bagdia |
| 2015-05-05 | cpu: Change literal integer constants to meaningful labels | Rekai Gonzalez Alberquilla |
| 2015-11-27 | base: Add support for changing output directories | Andreas Sandberg |
| 2015-08-10 | mem, cpu: Add assertions to snoop invalidation logic | Stephan Diestelhorst |
| 2015-07-19 | cpu: Fix LLSC atomic CPU wakeup | Krishnendra Nathella |
| 2016-02-10 | mem: Deduce if cache should forward snoops | Andreas Hansson |
| 2016-02-06 | style: fix missing spaces in control statements | Steve Reinhardt |
| 2016-02-06 | style: remove trailing whitespace | Steve Reinhardt |
| 2016-01-17 | cpu: remove unnecessary data ptr from O3 internal read() funcs | Steve Reinhardt |
| 2015-12-31 | mem: Make cache terminology easier to understand | Andreas Hansson |
| 2015-12-07 | cpu: Support virtual addr in elastic traces | Radhika Jagtap |
| 2015-12-07 | cpu: Create record type enum for elastic traces | Radhika Jagtap |
| 2015-12-07 | proto, probe: Add elastic trace probe to o3 cpu | Radhika Jagtap |
| 2015-12-07 | probe: Add probe in Fetch, IEW, Rename and Commit | Radhika Jagtap |
| 2015-12-04 | cpu: fix unitialized variable which may cause assertion failure | Pau Cabre |
| 2015-11-22 | cpu: Fix base FP and CC register index in o3 insertThread() | Nathanael Premillieu |
| 2015-11-16 | o3: drop unused statistic wbPenalized and wbPenalizedRate | Nilay Vaish |
| 2015-10-12 | misc: Add explicit overrides and fix other clang >= 3.5 issues | Andreas Hansson |
| 2015-10-12 | misc: Remove redundant compiler-specific defines | Andreas Hansson |
| 2015-10-09 | isa: Add parameter to pick different decoder inside ISA | Rekai Gonzalez Alberquilla |
| 2015-09-30 | cpu,isa,mem: Add per-thread wakeup logic | Mitch Hayenga |
| 2015-09-30 | isa,cpu: Add support for FS SMT Interrupts | Mitch Hayenga |
| 2015-09-30 | cpu: Add per-thread monitors | Mitch Hayenga |
| 2015-09-15 | cpu, o3: consider split requests for LSQ checksnoop operations | Hongil Yoon |
| 2015-08-07 | base: Declare a type for context IDs | Andreas Sandberg |
| 2015-07-20 | cpu: Fixed a bug on where to fetch the next instruction from | David Hashe |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2015-07-26 | cpu: o3: slight correction to identation in rename_impl.hh | Nilay Vaish |
| 2015-07-07 | sim: Refactor and simplify the drain API | Andreas Sandberg |
| 2015-07-07 | sim: Make the drain state a global typed enum | Andreas Sandberg |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2015-07-04 | o3: correct the number of cc registers in rename map | Nilay Vaish |
| 2015-05-15 | misc: Appease gcc 5.1 | Andreas Hansson |
| 2015-05-05 | mem, cpu: Add a separate flag for strictly ordered memory | Andreas Sandberg |
| 2015-05-05 | mem: Snoop into caches on uncacheable accesses | Andreas Hansson |
| 2015-05-05 | cpu: Work around gcc 4.9 issues with Num_OpClasses | Andreas Hansson |
| 2015-04-29 | cpu: o3: replace issueLatency with bool pipelined | Nilay Vaish |
| 2015-04-29 | cpu: o3: single cycle default div microop latency on x86 | Nilay Vaish |
