summaryrefslogtreecommitdiff
path: root/src/cpu/o3
AgeCommit message (Expand)Author
2014-10-20cpu: o3: corrects base FP and CC register index in removeThread()Nilay Vaish
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
2014-10-16o3: Use shared_ptr for MemDepEntryAndreas Hansson
2014-10-16cpu: Probe points for basic PMU statsAndreas Sandberg
2014-10-11cpu: Fix o3 SMT IQCount bugAndrew Lukefahr
2014-10-09cpu: Remove Ozone CPU from the source treeMitch Hayenga
2014-09-27arch: Use const StaticInstPtr references where possibleAndreas Hansson
2014-09-20cpu: Remove unused deallocateContext callsMitch Hayenga
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-20base: Clean up redundant string functions and use C++11Andreas Hansson
2014-09-19arch: Pass faults by const reference where possibleAndreas Hansson
2014-09-19cpu: Use a deque in o3 rename instruction queueAndreas Hansson
2014-09-09cpu: Only iterate over possible threads on the o3 cpuMitch Hayenga
2014-05-13mem: Refactor assignment of Packet typesCurtis Dunham
2014-09-03cpu: Fix o3 drain bugMitch Hayenga
2014-04-29arm: use condition code registers for ARM ISACurtis Dunham
2014-09-03cpu: Fix cache blocked load behavior in o3 cpuMitch Hayenga
2014-09-03cpu: Fix o3 quiesce fetch bugMitch Hayenga
2014-09-03cpu: Fix SMT scheduling issue with the O3 cpuMitch Hayenga
2014-09-03cpu: Add a fetch queue to the o3 cpuMitch Hayenga
2014-09-03cpu: Fix o3 front-end pipeline interlock behaviorMitch Hayenga
2014-09-03cpu: Change writeback modeling for outstanding instructionsMitch Hayenga
2014-09-03arch, cpu: Factor out the ExecContext into a proper base classAndreas Sandberg
2014-06-30cpu: implement a bi-mode branch predictorAnthony Gutierrez
2014-06-21o3: make dispatch LSQ full check more selectiveBinh Pham
2014-06-21o3: split load & store queue full cases in renameBinh Pham
2014-05-31style: eliminate equality tests with true and falseSteve Reinhardt
2014-05-23cpu: o3: remove stat totalCommittedInstsNilay Vaish
2014-05-09cpu: add more instruction mix statisticsCurtis Dunham
2014-05-09cpu, arm: Allow the specification of a socket fieldAkash Bagdia
2014-04-01cpu: Fix case where o3 lsq could print out uninitialized dataMitch Hayenga
2014-04-23cpu: Add O3 CPU width checksDam Sunwoo
2014-04-19o3: Fix occupancy checks for SMTFaissal Sleiman
2014-03-25cpu: o3: lsq: Fix TSO implementationMarco Elver
2014-03-12alpha: Small removal of dead comments/code from alpha ISAPaul Rosenfeld
2014-03-07cpu: Make CPU and ThreadContext getters constAndreas Hansson
2014-03-07scons: Fixes uninitialized warnings issued by clangMitch Hayenga
2014-01-24checker: CheckerCPU handling of MiscRegs was incorrectGeoffrey Blake
2014-01-24arch, cpu: Add support for flattening misc register indexes.Ali Saidi
2014-01-24cpu: Add support for Memory+Barrier instruction types in O3 cpu.Giacomo Gabrielli
2014-01-24cpu: Add support for instructions that zero cache lines.Ali Saidi
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2014-01-24base: add support for probe points and common probesMatt Horsnell
2014-01-24mem: track per-request latencies and access depths in the cache hierarchyMatt Horsnell
2014-01-24cpu: Relax check on squashed non-speculative instructionsAndreas Hansson
2013-12-03cpu: call BaseCPU startup() function in o3 cpuNilay Vaish
2013-11-15cpu: allow the fetch buffer to be smaller than a cache lineAnthony Gutierrez
2013-10-31cpu: Construct ROB with cpu params struct instead of each variableFaissal Sleiman
2013-10-31cpu: Fix O3 issuse with load+barrier instructions.Ali Saidi
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-26 20:04:30 +0000