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path: root/src/cpu/o3
AgeCommit message (Expand)Author
2007-04-22Use proper cycles for IPC and CPI equations.Kevin Lim
2007-04-09Merge ktlim@zizzer:/bk/newmemKevin Lim
2007-04-09Fix bug when blocking due to no free registers.Kevin Lim
2007-04-08Take into account that the flattened integer register space is a different si...Gabe Black
2007-04-08Get the "hard" SPARC instructions working in o3. I don't like that the IsStor...Gabe Black
2007-04-04Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-04-04Updates for other ISA cpu_builders.Kevin Lim
2007-04-04Pass ISA-specific O3 CPU as a constructor parameter instead of using setCPU f...Kevin Lim
2007-04-03Made the "data" field of store queue entries into a character array. It's siz...Gabe Black
2007-04-03Fix a memory leak. Hopefully this fixes the longer running benchmarks.Kevin Lim
2007-04-02Remove/comment out DPRINTFs that were causing a segfault.Kevin Lim
2007-04-02Fix up SPARC's CPU builder to match changes to Alpha's CPU builder.Kevin Lim
2007-03-29Update code so that the O3 CPU can handle not initially having anything hooke...Kevin Lim
2007-03-24Update for new trace data behavior.Kevin Lim
2007-03-23Merge ktlim@zizzer:/bk/newmemKevin Lim
2007-03-23Updates for commit.Kevin Lim
2007-03-23Handle status bits a little better, as well as non-speculative instructions.Kevin Lim
2007-03-23Two fixes:Kevin Lim
2007-03-23A couple of minor fixes.Kevin Lim
2007-03-15Merge zizzer:/bk/newmemAli Saidi
2007-03-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-03-15Make the predecoder an object with it's own switched header file. Start addin...Gabe Black
2007-03-13fix segfault when peer owner attempts to use functional portAli Saidi
2007-03-13Replaced makeExtMI with predecode.Gabe Black
2007-03-10Rework the way SCons recurses into subdirectories, making itNathan Binkert
2007-03-09Two fixes:Kevin Lim
2007-03-07I missed a couple of WithEffects, this should do itAli Saidi
2007-03-07*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscRegAli Saidi
2007-03-06Move all of the parameters of the Root SimObject so they areNathan Binkert
2007-03-05Added an x86 dyninstGabe Black
2007-02-10Clean up tracing stuff more, get rid of the trace log sinceNathan Binkert
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
2007-01-29A minor hack to get branch prediction to behave like before on Alpha.Gabe Black
2007-01-29Fixed a warning about an unused variable.Gabe Black
2007-01-27Merge zizzer:/bk/newmemGabe Black
2007-01-26eliminate cpu checkInterrupts bool, it is redundant and unnecessary.Lisa Hsu
2007-01-03Merge zizzer:/bk/newmemGabe Black
2006-12-30Fix up previous commit to proper logic.Kevin Lim
2006-12-28Fixes to get non-delay slot ISAs (Alpha) working again, and pulling some debu...Gabe Black
2006-12-28Phased out DelaySlotInfo.Gabe Black
2006-12-28Some fixes for decode stage branches without delay slots. This will need some...Gabe Black
2006-12-28Make sure the value of PC is actually updated now that the instruction target...Gabe Black
2006-12-28Implement a stub nnpc for alpha that is read only as npc+4.Gabe Black
2006-12-26Remove some #if FULL_SYSTEMs so MP stuff works even in SE mode.Kevin Lim
2006-12-21styleNathan Binkert
2006-12-20don't use (*activeThreads).begin(), use activeThreads->blah().Nathan Binkert
2006-12-20<scold> Make sure that variables are always initalized! </scold>Nathan Binkert
2006-12-20Fixes to get MIPS_SE to compile.Gabe Black
2006-12-20Fixes to get ALPHA_FS and ALPHA_SE to compile again.Gabe Black
2006-12-18Fix a place where the wrong width parameter was used, and set the nextNPC cor...Gabe Black
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