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path: root/src/cpu/o3
AgeCommit message (Expand)Author
2006-10-09Comment out code that messed up SMT (but will be needed eventually).Kevin Lim
2006-10-09Be sure to delete packet and sender state if the cache is blocked.Kevin Lim
2006-10-09Fix caches plus sampling switch over.Kevin Lim
2006-10-09Fix outstanding bug (FS#158).Kevin Lim
2006-10-08Updates to O3 CPU. It should now work in FS mode, although sampling still ha...Kevin Lim
2006-10-02Updates to fix merge issues and bring almost everything up to working speed. ...Kevin Lim
2006-09-30Merge ktlim@zamp:./local/clean/o3-merge/m5Kevin Lim
2006-09-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2006-09-03Fix up the parameters to getInstRecordGabe Black
2006-08-31add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throug...Korey Sewell
2006-08-16Fixes for Kevins O3 model to work with the blocking caches.Ron Dreslinski
2006-08-15Some touchup to the reorganized includes and "using" directives.Gabe Black
2006-08-15Cleaned up include files and got rid of many using directives in header files.Gabe Black
2006-08-11Started to add support for O3 for sparc.Gabe Black
2006-08-11Pushed most of constants.hh back into isa_traits.hh and regfile.hh and create...Gabe Black
2006-07-26MIPS ISA runs 'hello world' in O3CPU ...Korey Sewell
2006-07-23This changeset gets the MIPS ISA pretty much working in the O3CPU. It builds,...Korey Sewell
2006-07-19O3CPU fixes.Kevin Lim
2006-07-19Some minor compiling fixes.Kevin Lim
2006-07-14Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-14forgot tidKorey Sewell
2006-07-14For now, halt context is the same as deallocating.Korey Sewell
2006-07-13Move Dcache port creation from LSQUnit to LSQ in order to support Ron's recen...Kevin Lim
2006-07-13Fix for bug when squashing and the fetching. Now fetch checks if the cache d...Kevin Lim
2006-07-13Update for changes to draining.Kevin Lim
2006-07-12Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-12Serialization changes to make O3CPU consistent with the other models.Kevin Lim
2006-07-12Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-12Track the PC of the cache data stored in fetch so it doesn't access memory mu...Kevin Lim
2006-07-11Fix ordering issue with squashed Icache Fetches and Static data in packet.Ron Dreslinski
2006-07-10Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-10Some minor cleanups.Kevin Lim
2006-07-10Add parameters for backwards and forwards sizes for time buffers.Kevin Lim
2006-07-07Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
2006-07-07Support Ron's changes for hooking up ports.Kevin Lim
2006-07-07Fix for bug when draining and a memory access is outstanding.Kevin Lim
2006-07-07Minor fix for SMT Hello Worlds to finish correctly.Korey Sewell
2006-07-07Switch out fixes for CPUs.Kevin Lim
2006-07-07Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
2006-07-07Fix so that O3CPU doesnt segfault on exit.Korey Sewell
2006-07-06Support serializing and unserializing in the O3 CPU. Also a few small fixes ...Kevin Lim
2006-07-06Fix the O3CPU to support the multi-pass method for checking if the system has...Kevin Lim
2006-07-06Various serialization changes to make it possible for the O3CPU to checkpoint.Kevin Lim
2006-07-06Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-07-06Support for draining, and the new method of switching out. Now switching out...Kevin Lim
2006-07-06Had to add this because for some reason gcc wasnt recognizing "THE_ISA == ALP...Korey Sewell
2006-07-06Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmemKorey Sewell
2006-07-06Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a s...Korey Sewell
2006-07-06more steps toward O3 SMTKorey Sewell
2006-07-05Remove sampler and serializer. Now they are handled through C++ interacting ...Kevin Lim
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