gem5 - gem5

Age	Commit message (Collapse)	Author
2011-07-10	O3: Fix up pipelining icache accesses in fetch stage to function properly	Geoffrey Blake
	Fixed up the patch from Yasuko Watanabe that enabled pipelining of fetch accessess to icache to work with recent changes to main repository. Also added in ability for fetch stage to delay issuing the fault carrying nop when a pipeline fetch causes a fault and no fetch bandwidth is available until the next cycle.
2011-07-10	O3: Make sure fetch doesn't go off into the weeds during speculation.	Ali Saidi

2011-06-10	o3: missing newlines on some dprintfs	Korey Sewell

2011-06-02	scons: rename TraceFlags to DebugFlags	Nathan Binkert

2011-05-23	O3: Fix offset calculation into storeQueue buffer for store->load forwarding	Geoffrey Blake
	Calculation of offset to copy from storeQueue[idx].data structure for load to store forwarding fixed to be difference in bytes between store and load virtual addresses. Previous method would induce bug where a load would index into buffer at the wrong location.
2011-05-23	O3: Fix issue w/wbOutstading being decremented multiple times on blocked cache.	Geoffrey Blake
	If a split load fails on a blocked cache wbOutstanding can be decremented twice if the first part of the split load succeeds and the second part fails. Condition the decrementing on not having completed the first part of the load.
2011-05-23	O3: Fix issue with interrupts/faults occuring in the middle of a macro-op	Geoffrey Blake
	This patch fixes two problems with the O3 cpu model. The first is an issue with an instruction fetch causing a fault on the next address while the current macro-op is being issued. This happens when the micro-ops exceed the fetch bandwdith and then on the next cycle the fetch stage attempts to issue a request to the next line while it still has micro-ops to issue if the next line faults a fault is attached to a micro-op in the currently executing macro-op rather than a "nop" from the next instruction block. This leads to an instruction incorrectly faulting when on fetch when it had no reason to fault. A similar problem occurs with interrupts. When an interrupt occurs the fetch stage nominally stops issuing instructions immediately. This is incorrect in the case of a macro-op as the current location might not be interruptable.
2011-05-13	O3: Fix an issue with a load & branch instruction and mem dep squashing	Geoffrey Blake
	Instructions that load an address and are control instructions can execute down the wrong path if they were predicted correctly and then instructions following them are squashed. If an instruction is a memory and control op use the predicted address for the next PC instead of just advancing the PC. Without this change NPC is used for the next instruction, but predPC is used to verify that the branch was successful so the wrong path is silently executed.
2011-05-04	O3: Remove assertion for case that is actually handled in code.	Ali Saidi
	If an nonspeculative instruction has a fault it might not be in the nonSpecInsts map.
2011-05-04	O3: Fix a small corner case with the lsq hazard detection logic.	Ali Saidi

2011-04-20	stats: one more name violation	Nathan Binkert

2011-04-19	stats: rename stats so they can be used as python expressions	Nathan Binkert

2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
	At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
2011-04-15	includes: fix up code after sorting	Nathan Binkert

2011-04-15	includes: sort all includes	Nathan Binkert

2011-04-04	ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.	Ali Saidi
	This change fixes a small bug in the arm copyRegs() code where some registers wouldn't be copied if the processor was in a mode other than MODE_USER. Additionally, this change simplifies the way the O3 switchCpu code works by utilizing TheISA::copyRegs() to copy the required context information rather than the adhoc copying that goes on in the CPU model. The current code makes assumptions about the visibility of int and float registers that aren't true for all architectures in FS mode.
2011-04-04	ARM: Cleanup implementation of ITSTATE and put important code in PCState.	Ali Saidi
	Consolidate all code to handle ITSTATE in the PCState object rather than touching a variety of structures/objects.
2011-04-04	CPU: Remove references to memory copy operations	Ali Saidi

2011-04-04	O3: Tighten memory order violation checking to 16 bytes.	Ali Saidi
	The comment in the code suggests that the checking granularity should be 16 bytes, however in reality the shift by 8 is 256 bytes which seems much larger than required.
2011-03-17	O3: Send instruction back to fetch on squash to seed predecoder correctly.	Ali Saidi

2011-03-17	O3: Cleanup the commitInfo comm struct.	Ali Saidi
	Get rid of unused members and use base types rather than derrived values where possible to limit amount of state.
2011-03-17	Mem: Fix issue with dirty block being lost when entire block transferred to ↵	Ali Saidi
	non-cache. This change fixes the problem for all the cases we actively use. If you want to try more creative I/O device attachments (E.g. sharing an L2), this won't work. You would need another level of caching between the I/O device and the cache (which you actually need anyway with our current code to make sure writes propagate). This is required so that you can mark the cache in between as top level and it won't try to send ownership of a block to the I/O device. Asserts have been added that should catch any issues.
2011-03-17	O3: Fix unaligned stores when cache blocked	Ali Saidi
	Without this change the a store can be issued to the cache multiple times. If this case occurs when the l1 cache is out of mshrs (and thus blocked) the processor will never make forward progress because each cycle it will send a single request using the recently freed mshr and not completing the multipart store. This will continue forever.
2011-02-25	O3CPU: Fix iqCount and lsqCount SMT fetch policies.	Timothy M. Jones
	Fixes two of the SMT fetch policies in O3CPU that were returning the count of instructions in the IQ or LSQ rather than the thread ID to fetch from.
2011-02-23	O3: When a prefetch causes a fault, don't record it in the inst	Ali Saidi

2011-02-23	O3: If there is an outstanding table walk don't let the inst queue sleep.	Ali Saidi
	If there is an outstanding table walk and no other activity in the CPU it can go to sleep and never wake up. This change makes the instruction queue always active if the CPU is waiting for a store to translate. If Gabe changes the way this code works then the below should be removed as indicated by the todo.
2011-02-23	ARM: Do something for ISB, DSB, DMB	Ali Saidi

2011-02-23	ARM: Fix bug that let two table walks occur in parallel.	Ali Saidi

2011-02-23	O3: Fix bug when a squash occurs right before TLB miss returns.	Ali Saidi
	In this case we need to throw away the TLB miss, not assume it was the one we were waiting for.
2011-02-13	O3: Fetch from the microcode ROM when needed.	Gabe Black

2011-02-13	O3: Fix GCC 4.2.4 complaint	Ali Saidi

2011-02-11	O3: Fix pipeline restart when a table walk completes in the fetch stage.	Giacomo Gabrielli
	When a table walk is initiated by the fetch stage, the CPU can potentially move to the idle state and never wake up. The fetch stage must call cpu->wakeCPU() when a translation completes (in finishTranslation()).
2011-02-11	O3: Enhance data address translation by supporting hardware page table walkers.	Giacomo Gabrielli
	Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, when a TLB miss occurs, initiateTranslation() can return with NoFault but with the translation unfinished. Instructions experiencing a delayed translation due to a hardware page table walk are deferred until the translation completes and kept into the IQ. In order to keep track of them, the IQ has been augmented with a queue of the outstanding delayed memory instructions. When their translation completes, instructions are re-executed (only their initiateAccess() was already executed; their DTB translation is now skipped). The IEW stage has been modified to support such a 2-pass execution.
2011-02-06	mcpat: Adds McPAT performance counters	Joel Hestness
	Updated patches from Rick Strong's set that modify performance counters for McPAT
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
	This makes sure that the address ranges requested for caches and uncached ports don't conflict with each other, and that accesses which are always uncached (message signaled interrupts for instance) don't waste time passing through caches.
2011-02-02	O3: Fix a style bug in O3.	Gabe Black

2011-02-01	X86: Add L1 caches for the TLB walkers.	Gabe Black
	Small L1 caches are connected to the TLB walkers when caches are used. This allows them to participate in the coherence protocol properly.
2011-01-18	O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.	Matt Horsnell

2011-01-18	O3: Don't test misprediction on load instructions until executed.	Matt Horsnell

2011-01-18	O3: Keep around the last committed instruction and use for squashing.	Ali Saidi
	Without this change 0 is always used for the youngest sequence number if a squash occured and the ROB was empty (E.g. an instruction is marked serializeAfter or a fetch stall prevents other instructions from issuing). Using 0 there is a race to rename where an instruction that committed the same cycle as the squashing instruction can have it's renamed state undone by the squash using sequence number 0.
2011-01-18	O3: Don't try to scoreboard misc registers.	Ali Saidi
	I'm not positive this is the correct fix, but it's working right now. Either we need to do something like this, prevent the misc reg from being renamed at all, or there something else going on. We need to find the root cause as to why this is only a problem sometimes.
2011-01-18	O3: Fix corner cases where multiple squashes/fetch redirects overwrite timebuf.	Matt Horsnell

2011-01-18	O3: Fix mispredicts from non control instructions.	Matt Horsnell
	The squash inside the fetch unit should not attempt to remove them from the branch predictor as non-control instructions are not pushed into the predictor.
2011-01-18	O3: Fixes the way prefetches are handled inside the iew unit.	Matt Horsnell
	This patch prevents the prefetch being added to the instCommit queue twice.
2011-01-18	O3: Support timing translations for O3 CPU fetch.	Ali Saidi

2011-01-18	ARM: Add support for moving predicated false dest operands from sources.	Ali Saidi

2011-01-18	O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.	Min Kyu Jeong
	When this condition occurs the cpu should restart the fetch stage to fetch from the original execution path. Fault handling in the commit stage is cleaned up a little bit so the control flow is simplier. Finally, if an instruction is being used to carry a fault it isn't executed, so the fault propagates appropriately.
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
	This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values.
2011-01-03	Move sched_list.hh and timebuf.hh from src/base to src/cpu.	Steve Reinhardt
	These files really aren't general enough to belong in src/base. This patch doesn't reorder include lines, leaving them unsorted in many cases, but Nate's magic script will fix that up shortly. --HG-- rename : src/base/sched_list.hh => src/cpu/sched_list.hh rename : src/base/timebuf.hh => src/cpu/timebuf.hh
2010-12-07	O3: Allow a store entry to store up to 16 bytes (instead of TheISA::IntReg).	Ali Saidi
	The store queue doesn't need to be ISA specific and architectures can frequently store more than an int registers worth of data. A 128 bits seems more common, but even 256 bits may be appropriate. Pretty much anything less than a cache line size is buildable.