summaryrefslogtreecommitdiff
path: root/src/cpu/o3
AgeCommit message (Expand)Author
2013-02-15cpu: Avoid duplicate entries in tracking structures for writes to misc regsGeoffrey Blake
2013-02-15cpu: Fix rename mis-handling serializing instructions when resource constrainedGeoffrey Blake
2013-02-15o3: fix tick used for renaming and issue with range selectionMatt Horsnell
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
2013-02-15cpu: Make checker CPUs inherit from CheckerCPU in the Python hierarchyAndreas Sandberg
2013-02-15cpu: Add CPU metadata om the Python classesAndreas Sandberg
2013-02-15cpu: include set in o3/commit_impl.Ali Saidi
2013-02-15cpu: fix case with o3 cpu blocking and unblocking decode in cycleAli Saidi
2013-02-15cpu: Fix a livelock in the o3 cpu.Ali Saidi
2013-01-24branch predictor: move out of o3 and inorder cpusNilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)
2013-01-22o3 cpu: fix zero reg problemAndrea Pellegrini
2013-01-22x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switchNilay Vaish
2013-01-19O3 IEW: Make incrWb and decrWb clearerJoel Hestness
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
2013-01-07cpu: Unify the serialization code for all of the CPU modelsAndreas Sandberg
2013-01-07cpu: Rewrite O3 draining to avoid stopping in microcodeAndreas Sandberg
2013-01-07cpu: Fix broken thread context handoverAndreas Sandberg
2013-01-07cpu: Fix O3 LSQ debug dumping constness and formattingAndreas Sandberg
2013-01-07cpu: Fix broken squashAfter implementation in O3 CPUAndreas Sandberg
2013-01-07o3 cpu: Remove unused variablesAndreas Sandberg
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07cpu: Correctly call parent on switchOut() and takeOverFrom()Andreas Sandberg
2013-01-07cpu: Unify SimpleCPU and O3 CPU serialization codeAndreas Sandberg
2013-01-07cpu: Initialize the O3 pipeline from startup()Andreas Sandberg
2013-01-07cpu: Implement a flat register interface in thread contextsAndreas Sandberg
2013-01-07cpu: Check that the memory system is in the correct modeAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-07o3: Fix issue with LLSC ordering and speculationAli Saidi
2013-01-07cpu: rename the misleading inSyscall to noSquashFromTCAli Saidi
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
2012-12-06TournamentBP: Fix some bugs with table sizes and countersErik Tomusk
2012-12-06o3 cpu: remove some unused buggy functions in the lsqNathanael Premillieu
2012-11-02sim: Move the draining interface into a separate base classAndreas Sandberg
2012-11-02cpu: O3 add a header declaring the DerivO3CPUAndreas Sandberg
2012-11-02cpu: Add header files for checker CPUsAndreas Sandberg
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-09-25O3: Pack the comm structures a bit better to reduce their size.Ali Saidi
2012-09-25CPU: Add abandoned instructions to O3 Pipe ViewerDjordje Kovacevic
2012-09-12stats: remove duplicate instruction stats from the commit stageAnthony Gutierrez
2012-09-07O3: Get rid of incorrect assert in RAS.Ali Saidi
2012-09-07Param: Transition to Cycles for relevant parametersAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-28Clock: Rework clocks to avoid tick-to-cycle transformationsAndreas Hansson
2012-08-22Packet: Remove NACKs from packet and its use in endpointsAndreas Hansson
2012-08-21CPU: Remove overloaded function_trace_start parameterAndreas Hansson
2012-08-21Clock: Make Tick unsigned and remove UTickAndreas Hansson
2012-08-15O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...Anthony Gutierrez
2012-07-27checker: make checker cpu id match its host's cpu idAnthony Gutierrez
2012-07-09Port: Align port names in C++ and PythonAndreas Hansson
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 23:01:10 +0000