gem5 - gem5

Age	Commit message (Expand)	Author
2013-01-12	x86: Changes to decoder, corrects 9376	Nilay Vaish
2013-01-07	cpu: Unify the serialization code for all of the CPU models	Andreas Sandberg
2013-01-07	cpu: Rewrite O3 draining to avoid stopping in microcode	Andreas Sandberg
2013-01-07	cpu: Fix broken thread context handover	Andreas Sandberg
2013-01-07	cpu: Fix O3 LSQ debug dumping constness and formatting	Andreas Sandberg
2013-01-07	cpu: Fix broken squashAfter implementation in O3 CPU	Andreas Sandberg
2013-01-07	o3 cpu: Remove unused variables	Andreas Sandberg
2013-01-07	cpu: Rename defer_registration->switched_out	Andreas Sandberg
2013-01-07	cpu: Correctly call parent on switchOut() and takeOverFrom()	Andreas Sandberg
2013-01-07	cpu: Unify SimpleCPU and O3 CPU serialization code	Andreas Sandberg
2013-01-07	cpu: Initialize the O3 pipeline from startup()	Andreas Sandberg
2013-01-07	cpu: Implement a flat register interface in thread contexts	Andreas Sandberg
2013-01-07	cpu: Check that the memory system is in the correct mode	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2013-01-07	o3: Fix issue with LLSC ordering and speculation	Ali Saidi
2013-01-07	cpu: rename the misleading inSyscall to noSquashFromTC	Ali Saidi
2013-01-04	Decoder: Remove the thread context get/set from the decoder.	Gabe Black
2012-12-06	TournamentBP: Fix some bugs with table sizes and counters	Erik Tomusk
2012-12-06	o3 cpu: remove some unused buggy functions in the lsq	Nathanael Premillieu
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-11-02	cpu: O3 add a header declaring the DerivO3CPU	Andreas Sandberg
2012-11-02	cpu: Add header files for checker CPUs	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-09-25	O3: Pack the comm structures a bit better to reduce their size.	Ali Saidi
2012-09-25	CPU: Add abandoned instructions to O3 Pipe Viewer	Djordje Kovacevic
2012-09-12	stats: remove duplicate instruction stats from the commit stage	Anthony Gutierrez
2012-09-07	O3: Get rid of incorrect assert in RAS.	Ali Saidi
2012-09-07	Param: Transition to Cycles for relevant parameters	Andreas Hansson
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-08-21	CPU: Remove overloaded function_trace_start parameter	Andreas Hansson
2012-08-21	Clock: Make Tick unsigned and remove UTick	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-07-27	checker: make checker cpu id match its host's cpu id	Anthony Gutierrez
2012-07-09	Port: Align port names in C++ and Python	Andreas Hansson
2012-07-09	Fix: Address a few benign memory leaks	Andreas Hansson
2012-06-29	O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.	Nathanael Premillieu
2012-06-05	ISA: Back-out NoopMachInst as a StaticInstPtr change.	Ali Saidi
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-06-04	ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.	Gabe Black
2012-05-26	CPU: Merge the predecoder and decoder.	Gabe Black
2012-05-25	Decode: Make the Decoder class defined per ISA.	Gabe Black
2012-05-01	MEM: Separate requests and responses for timing accesses	Andreas Hansson
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-14	MEM: Separate snoops and normal memory requests/responses	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-30	CPU: Unify initMemProxies across CPUs and simulation modes	Andreas Hansson