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2006-12-28Implement a stub nnpc for alpha that is read only as npc+4.Gabe Black
--HG-- extra : convert_revision : d08b740d32757fa5471c9bcde9084d59a1d8102d
2006-12-20Fixes to get MIPS_SE to compile.Gabe Black
--HG-- extra : convert_revision : d173f212841341e436e9a38dcd3006d27886c1b8
2006-12-20Fixes to get ALPHA_FS and ALPHA_SE to compile again.Gabe Black
--HG-- extra : convert_revision : 6e0913903d4cbda6f31bec3b5d725b9c08dc1419
2006-12-18Fix a place where the wrong width parameter was used, and set the nextNPC ↵Gabe Black
correctly on memory squashes. --HG-- extra : convert_revision : 7914a48ea953607c48f93984e3b043098f0d7c62
2006-12-18Make sure you only handle branch delay slots specially when there actually ↵Gabe Black
was a branch. --HG-- extra : convert_revision : ea6d33b1b9c2ba5c24225af4b10a9bd25558f1dd
2006-12-17Convert Alpha (and finish converting MIPS) to newSteve Reinhardt
InstObjParam interface. src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/fp.isa: src/arch/alpha/isa/int.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/isa/mem.isa: src/arch/alpha/isa/pal.isa: src/arch/mips/isa/formats/mem.isa: src/arch/mips/isa/formats/util.isa: Get rid of CodeBlock calls to adapt to new InstObjParam interface. src/arch/isa_parser.py: Check template code for operands (in addition to snippets). src/cpu/o3/alpha/dyn_inst.hh: Add (read|write)MiscRegOperand calls to Alpha DynInst. --HG-- extra : convert_revision : 332caf1bee19b014cb62c1ed9e793e793334c8ee
2006-12-16Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem src/arch/isa_parser.py: src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: src/cpu/o3/iew_impl.hh: Hand Merge --HG-- extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47
2006-12-16Switch the endianness of data that's forwarded. This is the same sort of ↵Gabe Black
problem that was happening when stores went all the way to memory and back. --HG-- extra : convert_revision : 09fece7ae934f542e51046d33505df3f7ec0b919
2006-12-16Make fetch detect when a branch is happening, rather than trying to compute ↵Gabe Black
when. --HG-- extra : convert_revision : 1a8edc004570abb48e6c4cdf1b43c5699866838e
2006-12-16Don't have "predict" set the predicted target of the instruction. Do that ↵Gabe Black
explicitly when you use predict. --HG-- extra : convert_revision : 8b613bb365b31ffaef1cea9fd789abe46219bdcf
2006-12-16Add in capability to return to unblocking after a squash. This is needed ↵Gabe Black
because if you don't squash -all- the instructions, you need to keep clearing out whatever is left in the skid buffer. --HG-- extra : convert_revision : 7308eda27f4366348cf5fce71ddfa4b217bc172d
2006-12-16Make sure endian conversion is done on the memory data when it's just set to ↵Gabe Black
an existing buffer. --HG-- extra : convert_revision : 5a890091b6a31b5414acbf68f19e28d7122a98d7
2006-12-16Make the decoder use the new setup in the dyninsts for branch prediction.Gabe Black
--HG-- extra : convert_revision : 9a6d6c93e5b40a55774891df54d290ff557b322c
2006-12-16Made branch delay slots get squashed, and passed back an NPC and NNPC to ↵Gabe Black
start fetching from. --HG-- extra : convert_revision : a2e4845fedf113b5a2fd92d3d28ce5b006278103
2006-12-16Changes to the isa_parser and affected files to fix an indexing problem with ↵Gabe Black
split execute instructions and miscregs aliasing with integer registers. src/arch/isa_parser.py: Rearranged things so that classes with more than one execute function treat operands properly. 1. Eliminated the CodeBlock class 2. Created a SubOperandList 3. Redefined how InstObjParams is constructed To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions. Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays. src/arch/sparc/isa/formats/basic.isa: src/arch/sparc/isa/formats/branch.isa: src/arch/sparc/isa/formats/integerop.isa: src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/isa/formats/nop.isa: src/arch/sparc/isa/formats/priv.isa: src/arch/sparc/isa/formats/trap.isa: Rearranged to work with new InstObjParam scheme. src/cpu/o3/sparc/dyn_inst.hh: Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays. src/cpu/simple/base.hh: Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. --HG-- extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
2006-12-15little fixes i noticed while searching for reason for address range issues ↵Lisa Hsu
(but these weren't the cause of the problem). RangeSize as a function takes a start address, and a SIZE, and will make the range (start, start+size-1) for you. src/cpu/memtest/memtest.hh: src/cpu/o3/fetch.hh: src/cpu/o3/lsq.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/simple/atomic.hh: src/cpu/simple/timing.hh: Fix RangeSize arguments src/dev/alpha/tsunami_cchip.cc: src/dev/alpha/tsunami_io.cc: src/dev/alpha/tsunami_pchip.cc: src/dev/baddev.cc: pioSize indicates SIZE, not a mask --HG-- extra : convert_revision : d385521fcfe58f8dffc8622260937e668a47a948
2006-12-13Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : 82733f9c7bf833cf6bbfbd2aad292f69f52d21bc
2006-12-12Merge zizzer:/bk/newmemLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/sparc/m5 --HG-- extra : convert_revision : 6e58629b1e51f1fc493a89f16c3f2e676dc5d191
2006-12-12Merge zizzer:/bk/newmem/Gabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem --HG-- extra : convert_revision : 17d6c49ee15af5d192dedf82871159219d4277cd
2006-12-12Merge ktlim@zizzer:/bk/newmemKevin Lim
into zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/test-regress --HG-- extra : convert_revision : d420ee86454b72b0e5d3a98bac3b496f172c1788
2006-12-12Allow for multiple redirects to happen on a single cycle (only the one for ↵Kevin Lim
the oldest instruction is passed on to commit). This fixes a minor bug when multiple FU completions come back out of order (due to the order in which the FUs are freed up), and the oldest redirect isn't recorded properly. The eon benchmark should run now. src/cpu/o3/iew_impl.hh: Allow for multiple redirects to happen on a single cycle (only the one for the oldest instruction is passed on to commit). --HG-- extra : convert_revision : b7d202dee1754539ed814f0fac59adb8c6328ee1
2006-12-12Rename the StaticInst-based (read|set)(Int|Float)Reg methods to ↵Steve Reinhardt
(read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version. --HG-- extra : convert_revision : b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
2006-12-11Fix up in case a req hasn't yet been generated for this instruction (if ↵Kevin Lim
there was a fault prior to translation). --HG-- extra : convert_revision : 43f4ea5e6a234cc6071006eab72135c11b8523c8
2006-12-11Fix for fetch to use the icache's block size to generate proper access size.Kevin Lim
--HG-- extra : convert_revision : 0f292233ac05b584f527c32f80e3ca3d40a6a2c1
2006-12-07Compilation fixesGabe Black
--HG-- extra : convert_revision : 974e91a960251a35d5ebb76c7e6c7ac330339896
2006-12-07Fix for squashing during a serializing instruction.Gabe Black
--HG-- extra : convert_revision : 04f9131258bfb7cca1654e00273edb29bde2366b
2006-12-06Fix for MIPS_SE/m5.fast compile.Kevin Lim
--HG-- extra : convert_revision : dbb893250974ac6db7b6c1ba67263fd35098ca43
2006-12-06Use the renamed register index, rather than the flattened one.Gabe Black
--HG-- extra : convert_revision : 599650c408667bb1b8db20a6847b9e697f7b49e4
2006-12-06Got rid of some typedefs and moved the tlbs into the base o3 cpu.Gabe Black
--HG-- extra : convert_revision : dcd1d2a64fd91aded15c8c763a78b4eebf421870
2006-12-06Use the setSyscallReturn defined in arch rather than duplicating it here.Gabe Black
--HG-- extra : convert_revision : 862ece59aa253b52b6744a0a76738d5ee19561b3
2006-12-06Moved the RegIdx arrays to the base dyninst.Gabe Black
--HG-- extra : convert_revision : d705cde25c2cf1add20669e99d086add49141518
2006-12-06Got rid of some typedefs, moved the tlbs to the base o3 cpu, and called the ↵Gabe Black
architecture defined setSyscallReturn function instead of a duplicate copy. src/cpu/o3/alpha/cpu.hh: Got rid of some typedefs, and moved the tlbs to the base o3 cpu. src/cpu/o3/alpha/thread_context.hh: src/cpu/o3/cpu.cc: Moved the tlbs to the base o3 cpu. --HG-- extra : convert_revision : 1805613aa230b8974a226ee3d2584c85f7a578aa
2006-12-06Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem src/cpu/o3/commit_impl.hh: Hand Merge --HG-- extra : convert_revision : 6984db90d5b5ec71c31f1c345f5a77eed540059e
2006-12-06Added a DPRINTF to print out the actual value pulled from memory.Gabe Black
--HG-- extra : convert_revision : 18780f753a7e98f8de3047dd6781b944b0826b4e
2006-12-06Flattening and syscallReturn fixesGabe Black
src/cpu/o3/thread_context_impl.hh: Use flattened indices src/cpu/simple_thread.hh: Use flattened indices, and pass a thread context to setSyscallReturn rather than a register file. src/cpu/thread_context.hh: The SyscallReturn class is no longer in arch/syscallreturn.hh --HG-- extra : convert_revision : ed84bb8ac5ef0774526ecd0d7270b0c60cd3708e
2006-12-06Don't panic, but this needs to be fixed.Gabe Black
--HG-- extra : convert_revision : 7a4aed238d437dbb2cc5946b3045d53697070a27
2006-12-06Make syscalls flatten their register indices, and also call into the ISA's ↵Gabe Black
setSyscallReturn function rather than having a duplicated one. --HG-- extra : convert_revision : 1e83ef629a7fd143f2e35e68abaa56f81d6b9d9e
2006-12-06Change rename to rename the flattened register index instead of the ↵Gabe Black
architectural one. --HG-- extra : convert_revision : 757866ad7a3c8be7382e1ffa71c60bc00c861f6f
2006-12-06Added in endianness conversion on memory accesses as the data goes out. This ↵Gabe Black
will break the checker! --HG-- extra : convert_revision : b8191cab09ab8f3ced05693293f058382319ed8e
2006-12-06Change how optional delay slot instructions are detected and squashed.Gabe Black
--HG-- extra : convert_revision : ffd019d4adc2fbbc0a663d8dc6ef73edce12511b
2006-12-06Get rid of some typedefs which were hardly used, and move some stuff back ↵Gabe Black
here that shouldn't be in the architecture specific DynInst classes. --HG-- extra : convert_revision : dad0d7191acf773c16dc3ed9dd911f5e8bfc08b3
2006-12-02Fixes for MIPS_SE compiling. Regressions seem to work, but Korey should ↵Kevin Lim
make sure these changes (commit especially) work okay. src/cpu/o3/commit_impl.hh: src/cpu/o3/fetch_impl.hh: Fixes for MIPS_SE compile. --HG-- extra : convert_revision : fde9616f8e72b397c5ca965774172372cff53790
2006-11-29Merge zizzer:/bk/sparcfsGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmemmid src/arch/sparc/isa_traits.hh: src/arch/sparc/miscregfile.hh: hand merge --HG-- extra : convert_revision : 34f50dc5e6e22096cb2c08b5888f2b0fcd418f3e
2006-11-29Change the connecting of the physPort and virtPort to the memory object ↵Kevin Lim
below the CPU to happen every time activateContext is called. The overhead is probably a little higher than necessary, but allows these connections to properly be made when there are CPUs that are inactive until they are switched in. Right now this introduces a minor memory leak as old physPorts and virtPorts are not deleted when new ones are created. A flyspray task has been created for this issue. It can not be resolved until we determine how the bus will handle giving out ID's to functional ports that may be deleted. src/cpu/o3/cpu.cc: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Change the setup of the physPort and virtPort to instead happen every time the CPU has a context activated. This is a little high overhead, but keeps it working correctly when the CPU does not have a physical memory attached to it until it switches in (like the case of switch CPUs). src/cpu/o3/thread_context.hh: Change function from being called at init() to just being called whenever the memory ports need to be connected. src/cpu/o3/thread_context_impl.hh: Update this to not delete the port if it's the same as the virtPort. src/cpu/thread_context.hh: Change function from being called at init() to whenever the memory ports need to be connected. src/cpu/thread_state.cc: Instead of initializing the ports, simply connect them, deleting any old ports that might exist. This allows these functions to be called multiple times. src/cpu/thread_state.hh: Ports are no longer initialized, but rather connected at context activation time. --HG-- extra : convert_revision : e399ce5dfbd6ad658c953a7c9c7b69b89a70219e
2006-11-24Initial changes to get O3 working with SPARCGabe Black
src/arch/sparc/process.cc: MachineBytes doesn't exist any more. src/arch/sparc/regfile.cc: Add in the miscRegFile for good measure. src/cpu/o3/isa_specific.hh: Add in a section for SPARC src/cpu/o3/sparc/cpu.cc: src/cpu/o3/sparc/cpu.hh: src/cpu/o3/sparc/cpu_builder.cc: src/cpu/o3/sparc/cpu_impl.hh: src/cpu/o3/sparc/dyn_inst.cc: src/cpu/o3/sparc/dyn_inst.hh: src/cpu/o3/sparc/dyn_inst_impl.hh: src/cpu/o3/sparc/impl.hh: src/cpu/o3/sparc/params.hh: src/cpu/o3/sparc/thread_context.cc: src/cpu/o3/sparc/thread_context.hh: Sparc version of this file. --HG-- extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
2006-11-19Update Virtual and Physical ports.Kevin Lim
src/cpu/o3/alpha/cpu_impl.hh: Handle the PhysicalPort and VirtualPort in the ThreadState. src/cpu/o3/cpu.cc: Initialize the thread context. src/cpu/o3/thread_context.hh: Add new function to initialize thread context. src/cpu/o3/thread_context_impl.hh: Use code now put into function. src/cpu/simple_thread.cc: Move code to ThreadState and use the new helper function. src/cpu/simple_thread.hh: Remove init() in this derived class; use init() from ThreadState base class. src/cpu/thread_state.cc: Move setting up of Physical and Virtual ports here. Change getMemFuncPort() to connectToMemFunc(), which connects a port to a functional port of the memory object below the CPU. src/cpu/thread_state.hh: Update functions. --HG-- extra : convert_revision : ff254715ef0b259dc80d08f13543b63e4024ca8d
2006-11-14Make cpu's capable of having a phase shiftRon Dreslinski
--HG-- extra : convert_revision : 7f082ba5c1cd2445aec731950c31a877aac23a75
2006-11-13Make CPU models signal to update the snoop rangesRon Dreslinski
--HG-- extra : convert_revision : 717b62510f28a69af99453309fbbb458359eeb2a
2006-11-13More interrupt reworking.Kevin Lim
--HG-- extra : convert_revision : 40dfbb72c4e418c54e909c54dad5fe6ef7017cb4
2006-11-13Change warn to DPRINTF.Kevin Lim
--HG-- extra : convert_revision : 746bdf92334d220158eb0eb6bf113b4dcedbb354
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