| Age | Commit message (Expand) | Author |
|---|
| 2016-02-06 | style: fix missing spaces in control statements | Steve Reinhardt |
| 2016-02-06 | style: remove trailing whitespace | Steve Reinhardt |
| 2016-01-17 | cpu: remove unnecessary data ptr from O3 internal read() funcs | Steve Reinhardt |
| 2015-12-31 | mem: Make cache terminology easier to understand | Andreas Hansson |
| 2015-12-07 | cpu: Support virtual addr in elastic traces | Radhika Jagtap |
| 2015-12-07 | cpu: Create record type enum for elastic traces | Radhika Jagtap |
| 2015-12-07 | proto, probe: Add elastic trace probe to o3 cpu | Radhika Jagtap |
| 2015-12-07 | probe: Add probe in Fetch, IEW, Rename and Commit | Radhika Jagtap |
| 2015-12-04 | cpu: fix unitialized variable which may cause assertion failure | Pau Cabre |
| 2015-11-22 | cpu: Fix base FP and CC register index in o3 insertThread() | Nathanael Premillieu |
| 2015-11-16 | o3: drop unused statistic wbPenalized and wbPenalizedRate | Nilay Vaish |
| 2015-10-12 | misc: Add explicit overrides and fix other clang >= 3.5 issues | Andreas Hansson |
| 2015-10-12 | misc: Remove redundant compiler-specific defines | Andreas Hansson |
| 2015-10-09 | isa: Add parameter to pick different decoder inside ISA | Rekai Gonzalez Alberquilla |
| 2015-09-30 | cpu,isa,mem: Add per-thread wakeup logic | Mitch Hayenga |
| 2015-09-30 | isa,cpu: Add support for FS SMT Interrupts | Mitch Hayenga |
| 2015-09-30 | cpu: Add per-thread monitors | Mitch Hayenga |
| 2015-09-15 | cpu, o3: consider split requests for LSQ checksnoop operations | Hongil Yoon |
| 2015-08-07 | base: Declare a type for context IDs | Andreas Sandberg |
| 2015-07-20 | cpu: Fixed a bug on where to fetch the next instruction from | David Hashe |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2015-07-26 | cpu: o3: slight correction to identation in rename_impl.hh | Nilay Vaish |
| 2015-07-07 | sim: Refactor and simplify the drain API | Andreas Sandberg |
| 2015-07-07 | sim: Make the drain state a global typed enum | Andreas Sandberg |
| 2015-07-07 | sim: Refactor the serialization base class | Andreas Sandberg |
| 2015-07-04 | o3: correct the number of cc registers in rename map | Nilay Vaish |
| 2015-05-15 | misc: Appease gcc 5.1 | Andreas Hansson |
| 2015-05-05 | mem, cpu: Add a separate flag for strictly ordered memory | Andreas Sandberg |
| 2015-05-05 | mem: Snoop into caches on uncacheable accesses | Andreas Hansson |
| 2015-05-05 | cpu: Work around gcc 4.9 issues with Num_OpClasses | Andreas Hansson |
| 2015-04-29 | cpu: o3: replace issueLatency with bool pipelined | Nilay Vaish |
| 2015-04-29 | cpu: o3: single cycle default div microop latency on x86 | Nilay Vaish |
| 2015-04-22 | cpu: remove conditional check (count > 0) on o3 IQ squashes | Brandon Potter |
| 2015-04-13 | cpu: re-organizes the branch predictor structure. | Dibakar Gope |
| 2015-04-03 | cpu: fix system total instructions accounting | Nikos Nikoleris |
| 2015-03-09 | cpu: o3: another assert instead of check | Nilay Vaish |
| 2015-03-09 | cpu: o3: Remove unused code in iew, add assert instead. | Nilay Vaish |
| 2015-03-09 | cpu: o3: commit: mark pipeline delay variable as consts | Nilay Vaish |
| 2015-03-09 | cpu: o3: remove unused stat variables. | Nilay Vaish |
| 2015-03-09 | cpu: o3: combine if with same condition | Nilay Vaish |
| 2015-03-09 | cpu: o3: remove member variable squashCounter | Nilay Vaish |
| 2015-03-09 | cpu: o3: remove unused function annotateMemoryUnits() | Nilay Vaish |
| 2015-03-02 | cpu: o3 register renaming request handling improved | Rekai |
| 2015-03-02 | mem: Split port retry for all different packet classes | Andreas Hansson |
| 2015-02-16 | arch: Make readMiscRegNoEffect const throughout | Andreas Hansson |
| 2015-02-06 | cpu: Idle CPU status logic revised | Alexandru Dutu |
| 2015-01-25 | cpu: Remove all notion that we know when the cpu is misspeculating. | Ali Saidi |
| 2014-12-05 | cpu: Only check for PC events on instruction boundaries. | Gabe Black |
| 2014-12-02 | cpu, o3: Ignored invalidate causing same-address load reordering | Marco Elver |
