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path: root/src/cpu/o3
AgeCommit message (Expand)Author
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2019-02-08cpu: support atomic memory request type with AtomicOpFunctorTuan Ta
2019-02-08sim,cpu: make exit_group halt all threads in a groupTuan Ta
2019-02-08cpu: fixed how O3 CPU executes an exit system callTuan Ta
2019-02-05misc: added missing override specifierAndrea Mondelli
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-25cpu, arch, arch-arm: Wire unused VecElem code in the O3 modelGiacomo Travaglini
2019-01-25cpu: O3 rename using the flatIndex instead of indexGiacomo Travaglini
2019-01-25cpu: Fix VecElemClass bugs in cpu modelsGiacomo Travaglini
2019-01-24cpu-o3: O3 LSQ GeneralisationRekai Gonzalez-Alberquilla
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
2019-01-17cpu-o3: Make the smtCommitPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtROBPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtIQPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtLSQPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-17cpu-o3: Make the smtFetchPolicy a Param.ScopedEnumNikos Nikoleris
2019-01-16cpu: dev: sim: gpu-compute: Banish some ISA specific register types.Gabe Black
2019-01-15cpu: Fix usage of setArchVecElemGiacomo Travaglini
2018-12-22cpu: Stop using unions to store FP registers.Gabe Black
2018-12-20arch, cpu: Remove float type accessors.Gabe Black
2018-12-11cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctorTony Gutierrez
2018-12-03cpu: Change raw pointers to STL ContainersRekai Gonzalez-Alberquilla
2018-11-28cpu,arch-arm: Initialise data membersRekai Gonzalez-Alberquilla
2018-11-27arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.Gabe Black
2018-11-16cpu: Fix the usage of const DynInstPtrRekai Gonzalez-Alberquilla
2018-08-10cpu: Removed unnecessary file reg_class_impl.hhBradley Wang
2018-07-24cpu-o3: Missing freeing the heads of DepGraph in IQ squashingHanhwi Jang
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
2018-03-27cpu: Remove ExtMachInst typedefs from the O3 CPU model.Gabe Black
2018-03-06scons: Switch from the print statement to the print function.Gabe Black
2018-02-20cpu-o3: Don't add non-speculative mem barriers to the IQ twiceAndreas Sandberg
2018-01-10style: change C/C++ source permissions to noexecBKP
2018-01-10alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.Gabe Black
2018-01-09cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults.Gabe Black
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
2017-12-22cpu: Use the generic nop static inst instead of decoding the arch version.Gabe Black
2017-12-13cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.Gabe Black
2017-12-05cpu: Add support for CMOs in the cpu modelsNikos Nikoleris
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
2017-11-28cpu-o3: Add missing vector stat initializersAndreas Sandberg
2017-11-21cpu, cpu, sim: move Cycle probe updateJose Marinho
2017-11-21cpu-o3: Prevent cpu from suspending if it is already drainingNikos Nikoleris
2017-11-20pwr: Adds logic to enter power gating for the cpu modelAnouk Van Laer
2017-11-14cpu, probe: Fix elastic trace register dependencyRadhika Jagtap
2017-10-19cpu-o3: Add M5_VAR_USED to variableJason Lowe-Power
2017-10-13cpu-o3: Check predication before the SQ size for a debug printNikos Nikoleris
2017-10-13cpu-o3: Avoid early checker verification for store conditionalsNikos Nikoleris