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path: root/src/cpu/o3
AgeCommit message (Expand)Author
2019-10-25cpu,sim: Delegate PCEvent scheduling from Systems to ThreadContexts.Gabe Black
2019-10-25cpu: Make the ThreadContext a PCEventScope.Gabe Black
2019-10-25cpu: Pass the address to check into the PCEventQueue service method.Gabe Black
2019-10-23cpu: Apply the ARM TLB rework to the O3 checker CPU.Gabe Black
2019-10-17cpu: Get rid of load count based events.Gabe Black
2019-10-15sim,cpu: Get rid of the unused instEventQueue.Gabe Black
2019-09-24cpu: Fix checker cpu instantiationNikos Nikoleris
2019-09-23cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>Jordi Vaquero
2019-08-28cpu: Make get(Data|Inst)Port return a Port and not a MasterPort.Gabe Black
2019-08-28cpu: Move the instruction port into o3's fetch stage.Gabe Black
2019-08-28cpu: Move O3's data port into the LSQ.Gabe Black
2019-08-07cpu-o3: fix atomic instructions non-speculativeJordi Vaquero
2019-08-07cpu-o3: added _amo_op parameter in o3 LSQJordi Vaquero
2019-07-28cpu-o3: Fix too strict assert condition in writeback()Gabor Dozsa
2019-07-27cpu: Add first-/non-faulting load support to Minor and O3Gabor Dozsa
2019-07-16cpu: isDrained renamed to isCpuDrainedGiacomo Travaglini
2019-07-13cpu-o3: Set packet data type for IPR readPouya Fotouhi
2019-07-08cpu-o3: Reset fault status for mem access in pushRequestGabor Dozsa
2019-05-31cpu-o3: Increase LSQ buffer sizes to match max vector lengthGabor Dozsa
2019-05-30cpu-o3: Add support for pinned writesGiacomo Gabrielli
2019-05-30arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.Gabe Black
2019-05-30cpu, sim: Return PortProxy &s from all the proxy accessors.Gabe Black
2019-05-29cpu: Added correct return type for ROB::countInstsAndrea Mondelli
2019-05-18arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.Gabe Black
2019-05-11cpu,mem: Add support for partial loads/stores and wide mem. accessesGiacomo Gabrielli
2019-05-11cpu: Add a memory access predicateGiacomo Gabrielli
2019-04-30cpu: alpha: Delete all occurrances of the simPalCheck function.Gabe Black
2019-04-30cpu: Remove hwrei from the generic interfaces.Gabe Black
2019-04-30arch: cpu: Track kernel stats using the base ISA agnostic type.Gabe Black
2019-04-29cpu: Get rid of the (read|set)RegOtherThread methods.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-04-22cpu: Eliminate the ProxyThreadContext class.Gabe Black
2019-04-10cpu: O3 switchFreeList checking VecElems instead of FloatRegsGiacomo Travaglini
2019-04-03misc: Removed inconsistency in O3* debug msgsAndrea Mondelli
2019-04-03arch-mips: added missing override specifier (o3)Andrea Mondelli
2019-03-28cpu: Added a probe to notify the address of retired instructionsJavier Bueno
2019-03-14cpu: Refactor of Physical Register implementationAndrea Mondelli
2019-03-14arch-arm,cpu: Add initial support for Arm SVEGiacomo Gabrielli
2019-02-27misc: Segmentation Fault during O3PipeView executionAndrea Mondelli
2019-02-22cpu-o3: Add cache read ports limit to LSQGabor Dozsa
2019-02-19cpu: Add ISA* getter in Thread interfaceGiacomo Gabrielli
2019-02-15cpu: Fix fast build broken due to unused variableGiacomo Travaglini
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2019-02-08cpu: support atomic memory request type with AtomicOpFunctorTuan Ta
2019-02-08sim,cpu: make exit_group halt all threads in a groupTuan Ta
2019-02-08cpu: fixed how O3 CPU executes an exit system callTuan Ta
2019-02-05misc: added missing override specifierAndrea Mondelli
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
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