| Age | Commit message (Expand) | Author |
|---|
| 2019-03-14 | cpu: Refactor of Physical Register implementation | Andrea Mondelli |
| 2019-03-14 | arch-arm,cpu: Add initial support for Arm SVE | Giacomo Gabrielli |
| 2019-02-27 | misc: Segmentation Fault during O3PipeView execution | Andrea Mondelli |
| 2019-02-22 | cpu-o3: Add cache read ports limit to LSQ | Gabor Dozsa |
| 2019-02-19 | cpu: Add ISA* getter in Thread interface | Giacomo Gabrielli |
| 2019-02-15 | cpu: Fix fast build broken due to unused variable | Giacomo Travaglini |
| 2019-02-12 | python: Don't assume SimObjects live in the global namespace | Andreas Sandberg |
| 2019-02-08 | cpu: support atomic memory request type with AtomicOpFunctor | Tuan Ta |
| 2019-02-08 | sim,cpu: make exit_group halt all threads in a group | Tuan Ta |
| 2019-02-08 | cpu: fixed how O3 CPU executes an exit system call | Tuan Ta |
| 2019-02-05 | misc: added missing override specifier | Andrea Mondelli |
| 2019-02-01 | cpu, arch: Replace the CCReg type with RegVal. | Gabe Black |
| 2019-01-31 | arch: cpu: Rename *FloatRegBits* to *FloatReg*. | Gabe Black |
| 2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
| 2019-01-25 | cpu, arch, arch-arm: Wire unused VecElem code in the O3 model | Giacomo Travaglini |
| 2019-01-25 | cpu: O3 rename using the flatIndex instead of index | Giacomo Travaglini |
| 2019-01-25 | cpu: Fix VecElemClass bugs in cpu models | Giacomo Travaglini |
| 2019-01-24 | cpu-o3: O3 LSQ Generalisation | Rekai Gonzalez-Alberquilla |
| 2019-01-22 | arch: cpu: Stop passing around misc registers by reference. | Gabe Black |
| 2019-01-17 | cpu-o3: Make the smtCommitPolicy a Param.ScopedEnum | Nikos Nikoleris |
| 2019-01-17 | cpu-o3: Make the smtROBPolicy a Param.ScopedEnum | Nikos Nikoleris |
| 2019-01-17 | cpu-o3: Make the smtIQPolicy a Param.ScopedEnum | Nikos Nikoleris |
| 2019-01-17 | cpu-o3: Make the smtLSQPolicy a Param.ScopedEnum | Nikos Nikoleris |
| 2019-01-17 | cpu-o3: Make the smtFetchPolicy a Param.ScopedEnum | Nikos Nikoleris |
| 2019-01-16 | cpu: dev: sim: gpu-compute: Banish some ISA specific register types. | Gabe Black |
| 2019-01-15 | cpu: Fix usage of setArchVecElem | Giacomo Travaglini |
| 2018-12-22 | cpu: Stop using unions to store FP registers. | Gabe Black |
| 2018-12-20 | arch, cpu: Remove float type accessors. | Gabe Black |
| 2018-12-11 | cpu-o3: Fix bug in LSQUnit(uint32_t, uint32_t) ctor | Tony Gutierrez |
| 2018-12-03 | cpu: Change raw pointers to STL Containers | Rekai Gonzalez-Alberquilla |
| 2018-11-28 | cpu,arch-arm: Initialise data members | Rekai Gonzalez-Alberquilla |
| 2018-11-27 | arch, base, cpu, gpu, mem: Replace assert(0 or false with panic. | Gabe Black |
| 2018-11-16 | cpu: Fix the usage of const DynInstPtr | Rekai Gonzalez-Alberquilla |
| 2018-08-10 | cpu: Removed unnecessary file reg_class_impl.hh | Bradley Wang |
| 2018-07-24 | cpu-o3: Missing freeing the heads of DepGraph in IQ squashing | Hanhwi Jang |
| 2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
| 2018-06-11 | misc: Substitute pointer to Request with aliased RequestPtr | Giacomo Travaglini |
| 2018-03-27 | cpu: Remove ExtMachInst typedefs from the O3 CPU model. | Gabe Black |
| 2018-03-06 | scons: Switch from the print statement to the print function. | Gabe Black |
| 2018-02-20 | cpu-o3: Don't add non-speculative mem barriers to the IQ twice | Andreas Sandberg |
| 2018-01-10 | style: change C/C++ source permissions to noexec | BKP |
| 2018-01-10 | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. | Gabe Black |
| 2018-01-09 | cpu: Use the NotAnInst flag to avoid passing an inst to fetch faults. | Gabe Black |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-12-22 | cpu: Use the generic nop static inst instead of decoding the arch version. | Gabe Black |
| 2017-12-13 | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. | Gabe Black |
| 2017-12-05 | cpu: Add support for CMOs in the cpu models | Nikos Nikoleris |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-11-28 | cpu-o3: Add missing vector stat initializers | Andreas Sandberg |
| 2017-11-21 | cpu, cpu, sim: move Cycle probe update | Jose Marinho |
