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2010-02-26cpu_models: get rid of cpu_models.py and move the stuff into SConsNathan Binkert
2009-09-23arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hhNathan Binkert
2009-09-22python: Move more code into m5.util allow SCons to use that code.Nathan Binkert
Get rid of misc.py and just stick misc things in __init__.py Move utility functions out of SCons files and into m5.util Move utility type stuff from m5/__init__.py to m5/util/__init__.py Remove buildEnv from m5 and allow access only from m5.defines Rename AddToPath to addToPath while we're moving it to m5.util Rename read_command to readCommand while we're moving it Rename compare_versions to compareVersions while we're moving it. --HG-- rename : src/python/m5/convert.py => src/python/m5/util/convert.py rename : src/python/m5/smartdict.py => src/python/m5/util/smartdict.py
2009-08-01Fix setting of INST_FETCH flag for O3 CPU.Steve Reinhardt
It's still broken in inorder. Also enhance DPRINTFs in cache and physical memory so we can see more easily whether it's getting set or not.
2009-07-08Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.Gabe Black
2009-07-08Registers: Add a registers.hh file as an ISA switched header.Gabe Black
This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. --HG-- rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh
2009-07-08Registers: Get rid of the float register width parameter.Gabe Black
2009-06-04types: clean up types, especially signed vs unsignedNathan Binkert
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
--HG-- rename : src/sim/host.hh => src/base/types.hh
2009-04-20request: rename INST_READ to INST_FETCH.Steve Reinhardt
2009-04-19Mem: Change isLlsc to isLLSC.Gabe Black
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2009-04-15ThreadState: initialize status to Halted in constructor.Steve Reinhardt
This provides a common initial status for all threads independent of CPU model (unlike the prior situation where CPUs initialized threads to inconsistent states). This mostly matters for SE mode; in FS mode, ISA-specific startupCPU() methods generally handle boot-time initialization of thread contexts (since the right thing to do is ISA-dependent).
2009-04-15Get rid of the Unallocated thread context state.Steve Reinhardt
Basically merge it in with Halted. Also had to get rid of a few other functions that called ThreadContext::deallocate(), including: - InOrderCPU's setThreadRescheduleCondition. - ThreadContext::exit(). This function was there to avoid terminating simulation when one thread out of a multi-thread workload exits, but we need to find a better (non-cpu-centric) way.
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2009-03-05stats: Fix all stats usages to deal with template fixesNathan Binkert
2009-02-27Processes: Make getting and setting system call arguments part of a process ↵Gabe Black
object.
2009-02-25ISA: Replace the translate functions in the TLBs with translateAtomic.Gabe Black
2009-02-25CPU: Get rid of translate... functions from various interface classes.Gabe Black
2009-01-24cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep.Nathan Binkert
Make interrupts use the new wakeup method, and pull all of the interrupt stuff into the cpu base class so that only the wakeup code needs to be updated. I tried to make wakeup, wakeCPU, and the various other mechanisms for waking and sleeping a little more sane, but I couldn't understand why the statistics were changing the way they were. Maybe we'll try again some day.
2008-11-10O3CPU: Make the instcount debugging stuff per-cpu.Clint Smullen
This is to prevent the assertion from firing if you have a large multicore. Also make sure that it's not compiled in when NDEBUG is defined
2008-11-04get rid of all instances of readTid() and getThreadNum(). Unify and eliminateLisa Hsu
redundancies with threadId() as their replacement.
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate.
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch.
2008-10-21style: Use the correct m5 style for things relating to interrupts.Nathan Binkert
2008-10-20O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. ↵Ali Saidi
Removing hwrei causes the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal call sys and thus the translation fails because the user is attempting to access a super page address. Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs. Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were removed since a great deal of manual patching would be required to only remove the hwrei change.
2008-10-12Get rid of old RegContext code.Gabe Black
2008-10-12Turn Interrupts objects into SimObjects. Also, move local APIC state into ↵Gabe Black
x86's Interrupts object.
2008-10-11CPU: Eliminate the simPalCheck funciton.Gabe Black
2008-10-11CPU: Eliminate the hwrei function.Gabe Black
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers ↵Ali Saidi
should configure their editors to not insert tabs
2008-08-18Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was ↵Richard Strong
done to be consistent with its python type of a latency. In addition, the multiple definitions of profile in the different cpu models caused problems for intialization of the interval value. If a child class's profile value was defined, the parent BaseCPU::ProfileEvent interval field would be initialized with a garbage value. The fix was to remove the multiple redifitions of profile in the child CPU classes.
2008-07-01Remove delVirtPort() and make getVirtPort() only return cached version.Ali Saidi
2008-06-28Backed out changeset 94a7bb476fca: caused memory leak.Steve Reinhardt
2008-06-21Generate more useful error messages for unconnected ports.Steve Reinhardt
Force all non-default ports to provide a name and an owner in the constructor.
2008-03-24Don't FastAlloc MSHRs since we don't allocate them on the fly.Steve Reinhardt
--HG-- extra : convert_revision : 02775cfb460afe6df0df0938c62cccd93a71e775
2008-02-26TLB: Make a TLB base class and put a virtual demapPage function in it.Gabe Black
--HG-- extra : convert_revision : cc0e62a5a337fd5bf332ad33bed61c0d505a936f
2008-02-10Fix #include lines for renamed cache files.Steve Reinhardt
--HG-- extra : convert_revision : b5008115dc5b34958246608757e69a3fa43b85c5
2008-02-06Make the Event::description() a const functionStephen Hines
--HG-- extra : convert_revision : c7768d54d3f78685e93920069f5485083ca989c0
2007-10-31Traceflags: Add SCons function to created a traceflag instead of having one ↵Ali Saidi
file with them all. --HG-- extra : convert_revision : 427f6bd8f050861ace3bc0d354a1afa5fc8319e6
2007-10-02CPU: Make the cpuid parameter get set in SE mode as well.Gabe Black
--HG-- extra : convert_revision : bc47206acb683ebaaa31f57af79b4b8db64e4d31
2007-10-02CPU: Make sure the system parameter gets set in the cpu builders. Other ↵Gabe Black
parameters need to be fixed as well. --HG-- extra : convert_revision : 0401970a79855ee0a96eb29305346ce07b5c98ea
2007-09-28Rename cycles() function to ticks()Ali Saidi
--HG-- extra : convert_revision : 790eddb793d4f5ba35813d001037bd8601bd76a5
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
--HG-- extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
--HG-- extra : convert_revision : e06a950964286604274fba81dcca362d75847233
2007-07-26X86: Fix argument register indexing.Gabe Black
Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg. --HG-- extra : convert_revision : f448a3ca4d6adc3fc3323562870f70eec05a8a1f
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way. --HG-- extra : convert_revision : 7e722873e417cb3d696f2e34c35ff488b7bff4ed
2007-06-30Make CPU models use new LoadLockedReq/StoreCondReq commands.Steve Reinhardt
--HG-- extra : convert_revision : ab78d9d1d88c3698edfd653d71c8882e1272b781
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