Age | Commit message (Expand) | Author |
2009-09-23 | arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh | Nathan Binkert |
2009-09-22 | python: Move more code into m5.util allow SCons to use that code. | Nathan Binkert |
2009-08-01 | Fix setting of INST_FETCH flag for O3 CPU. | Steve Reinhardt |
2009-07-08 | Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. | Gabe Black |
2009-07-08 | Registers: Add a registers.hh file as an ISA switched header. | Gabe Black |
2009-07-08 | Registers: Get rid of the float register width parameter. | Gabe Black |
2009-06-04 | types: clean up types, especially signed vs unsigned | Nathan Binkert |
2009-05-26 | types: add a type for thread IDs and try to use it everywhere | Nathan Binkert |
2009-05-17 | includes: sort includes again | Nathan Binkert |
2009-05-17 | types: Move stuff for global types into src/base/types.hh | Nathan Binkert |
2009-04-20 | request: rename INST_READ to INST_FETCH. | Steve Reinhardt |
2009-04-19 | Mem: Change isLlsc to isLLSC. | Gabe Black |
2009-04-19 | Memory: Rename LOCKED for load locked store conditional to LLSC. | Gabe Black |
2009-04-15 | ThreadState: initialize status to Halted in constructor. | Steve Reinhardt |
2009-04-15 | Get rid of the Unallocated thread context state. | Steve Reinhardt |
2009-04-08 | tlb: Don't separate the TLB classes into an instruction TLB and a data TLB | Gabe Black |
2009-03-05 | stats: Fix all stats usages to deal with template fixes | Nathan Binkert |
2009-02-27 | Processes: Make getting and setting system call arguments part of a process o... | Gabe Black |
2009-02-25 | ISA: Replace the translate functions in the TLBs with translateAtomic. | Gabe Black |
2009-02-25 | CPU: Get rid of translate... functions from various interface classes. | Gabe Black |
2009-01-24 | cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep. | Nathan Binkert |
2008-11-10 | O3CPU: Make the instcount debugging stuff per-cpu. | Clint Smullen |
2008-11-04 | get rid of all instances of readTid() and getThreadNum(). Unify and eliminate | Lisa Hsu |
2008-11-02 | Add in Context IDs to the simulator. From now on, cpuId is almost never used, | Lisa Hsu |
2008-11-02 | make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered | Lisa Hsu |
2008-10-21 | style: Use the correct m5 style for things relating to interrupts. | Nathan Binkert |
2008-10-20 | O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Remo... | Ali Saidi |
2008-10-12 | Get rid of old RegContext code. | Gabe Black |
2008-10-12 | Turn Interrupts objects into SimObjects. Also, move local APIC state into x86... | Gabe Black |
2008-10-11 | CPU: Eliminate the simPalCheck funciton. | Gabe Black |
2008-10-11 | CPU: Eliminate the hwrei function. | Gabe Black |
2008-09-10 | style: Remove non-leading tabs everywhere they shouldn't be. Developers shoul... | Ali Saidi |
2008-08-18 | Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was ... | Richard Strong |
2008-07-01 | Remove delVirtPort() and make getVirtPort() only return cached version. | Ali Saidi |
2008-06-28 | Backed out changeset 94a7bb476fca: caused memory leak. | Steve Reinhardt |
2008-06-21 | Generate more useful error messages for unconnected ports. | Steve Reinhardt |
2008-03-24 | Don't FastAlloc MSHRs since we don't allocate them on the fly. | Steve Reinhardt |
2008-02-26 | TLB: Make a TLB base class and put a virtual demapPage function in it. | Gabe Black |
2008-02-10 | Fix #include lines for renamed cache files. | Steve Reinhardt |
2008-02-06 | Make the Event::description() a const function | Stephen Hines |
2007-10-31 | Traceflags: Add SCons function to created a traceflag instead of having one f... | Ali Saidi |
2007-10-02 | CPU: Make the cpuid parameter get set in SE mode as well. | Gabe Black |
2007-10-02 | CPU: Make sure the system parameter gets set in the cpu builders. Other param... | Gabe Black |
2007-09-28 | Rename cycles() function to ticks() | Ali Saidi |
2007-08-26 | Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. | Gabe Black |
2007-07-26 | Merge python and x86 changes with cache branch | Nathan Binkert |
2007-07-26 | X86: Fix argument register indexing. | Gabe Black |
2007-07-23 | Major changes to how SimObjects are created and initialized. Almost all | Nathan Binkert |
2007-06-30 | Make CPU models use new LoadLockedReq/StoreCondReq commands. | Steve Reinhardt |
2007-06-30 | Event descriptions should not end in "event" | Steve Reinhardt |