gem5 - gem5

Age	Commit message (Expand)	Author
2013-10-17	cpu: add consistent guarding to *_impl.hh files.	Matt Horsnell
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-10-15	cpu: rename _DepTag constants to _Reg_Base	Steve Reinhardt
2013-08-19	cpu: Accurately count idle cycles for simple cpu	Lena Olson
2013-01-07	cpu: Rename defer_registration->switched_out	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2013-01-07	cpu: rename the misleading inSyscall to noSquashFromTC	Ali Saidi
2012-08-21	CPU: Remove overloaded function_trace_start parameter	Andreas Hansson
2012-06-05	sim: Remove FastAlloc	Ali Saidi
2012-04-14	MEM: Remove the Broadcast destination from the packet	Andreas Hansson
2012-04-06	MEM: Enable multiple distributed generalized memories	Andreas Hansson
2012-03-30	MEM: Introduce the master/slave port sub-classes in C++	William Wang
2012-03-09	O3/Ozone: Eliminate dead code counting software prefetch insts	Geoffrey Blake
2012-03-09	CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable	Geoffrey Blake
2012-02-24	MEM: Make port proxies use references rather than pointers	Andreas Hansson
2012-02-07	Faults: Turn off arch/faults.hh	Gabe Black
2012-01-28	Merge with the main repo.	Gabe Black
2012-01-17	MEM: Separate queries for snooping and address ranges	Andreas Hansson
2012-01-17	MEM: Add port proxies instead of non-structural ports	Andreas Hansson
2011-11-18	SE/FS: Get rid of includes of config/full_system.hh.	Gabe Black
2011-11-18	SE/FS: Get rid of FULL_SYSTEM in the CPU directory.	Gabe Black
2011-10-30	SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs.	Gabe Black
2011-10-16	SE/FS: Include getMemPort in FS.	Gabe Black
2011-10-16	SE/FS: Build/expose vport in SE mode.	Gabe Black
2011-10-16	CPU: Make physPort and getPhysPort available in SE mode.	Gabe Black
2011-08-02	O3: Get rid of the raw ExtMachInst constructor on DynInsts.	Gabe Black
2011-06-02	scons: rename TraceFlags to DebugFlags	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-04-04	CPU: Remove references to memory copy operations	Ali Saidi
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2011-01-03	Move sched_list.hh and timebuf.hh from src/base to src/cpu.	Steve Reinhardt
2010-11-08	ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.	Ali Saidi
2010-09-13	CPU: Get rid of the now unnecessary getInst/setInst family of functions.	Gabe Black
2010-08-23	ISA: Get rid of old, unused utility functions cluttering up the ISAs.	Gabe Black
2010-06-14	stats: get rid of the never-really-used event stuff	Nathan Binkert
2010-06-03	Minor remote GDB cleanup.	Steve Reinhardt
2010-02-26	cpu_models: get rid of cpu_models.py and move the stuff into SCons	Nathan Binkert
2009-09-23	arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh	Nathan Binkert
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2009-08-01	Fix setting of INST_FETCH flag for O3 CPU.	Steve Reinhardt
2009-07-08	Get rid of the unused get(Data\|Inst)Asid and (inst\|data)Asid functions.	Gabe Black
2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black
2009-07-08	Registers: Get rid of the float register width parameter.	Gabe Black
2009-06-04	types: clean up types, especially signed vs unsigned	Nathan Binkert
2009-05-26	types: add a type for thread IDs and try to use it everywhere	Nathan Binkert
2009-05-17	includes: sort includes again	Nathan Binkert
2009-05-17	types: Move stuff for global types into src/base/types.hh	Nathan Binkert
2009-04-20	request: rename INST_READ to INST_FETCH.	Steve Reinhardt
2009-04-19	Mem: Change isLlsc to isLLSC.	Gabe Black
2009-04-19	Memory: Rename LOCKED for load locked store conditional to LLSC.	Gabe Black