gem5 - gem5

Age	Commit message (Expand)	Author
2019-05-13	cpu: Make the indirect predictor into a SimObject	Jairo Balart
2019-04-03	misc: Removed inconsistency in O3* debug msgs	Andrea Mondelli
2019-03-27	cpu: Fixed the indirect branch predictor GHR handling	Pau Cabre
2019-02-26	cpu: Fix indirect branch history updates	Srikant Bharadwaj
2019-02-08	cpu: Proposal for changing the indirect branch predictor interface	Jairo Balart
2019-02-05	cpu: Made TAGE a SimObject that can be used by other predictors	Jairo Balart
2016-12-21	cpu: disallow speculative update of branch predictor tables (o3)	Arthur Perais
2016-11-30	cpu: Remove branch predictor function predictInOrder	Jason Lowe-Power
2016-06-06	stats: Fixing regStats function for some SimObjects	David Guillen Fandos
2016-04-05	cpu: Implement per-thread GHRs	Mitch Hayenga
2016-04-05	cpu: Add an indirect branch target predictor	Mitch Hayenga
2016-04-05	cpu: Fix BTB threading oversight	Mitch Hayenga
2016-04-06	Revert power patch sets with unexpected interactions	Andreas Sandberg
2016-04-05	cpu: Implement per-thread GHRs	Curtis Dunham
2016-04-05	cpu: Add an indirect branch target predictor	Mitch Hayenga
2016-04-05	cpu: Fix BTB threading oversight	Mitch Hayenga
2016-02-06	style: fix missing spaces in control statements	Steve Reinhardt
2015-04-13	cpu: re-organizes the branch predictor structure.	Dibakar Gope
2014-06-30	cpu: implement a bi-mode branch predictor	Anthony Gutierrez
2013-01-24	branch predictor: move out of o3 and inorder cpus	Nilay Vaish ext:(%2C%20Timothy%20Jones%20%3Ctimothy.jones%40cl.cam.ac.uk%3E)