index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
cpu
/
pred
Age
Commit message (
Expand
)
Author
2019-05-18
arch, base, cpu, dev, mem, sim: Remove #if 0-ed out code.
Gabe Black
2019-05-14
base: Move SatCounter to base directory
Daniel
2019-05-14
cpu: Revamp saturating counters
Daniel
2019-05-13
cpu: Make the indirect predictor into a SimObject
Jairo Balart
2019-04-03
misc: Removed inconsistency in O3* debug msgs
Andrea Mondelli
2019-03-27
cpu: Fixed the indirect branch predictor GHR handling
Pau Cabre
2019-02-26
cpu: Fix indirect branch history updates
Srikant Bharadwaj
2019-02-13
cpu: Added 8KB and 64KB TAGE-SC-L branch predictor
Javier Bueno
2019-02-08
cpu: Proposal for changing the indirect branch predictor interface
Jairo Balart
2019-02-05
cpu: Made the Loop Predictor a SimObject
Javier Bueno
2019-02-05
cpu: Made TAGE a SimObject that can be used by other predictors
Jairo Balart
2018-12-11
cpu: Fixed typos in parameter/stats descriptions
Pau Cabre
2018-12-11
cpu: Added parameters to enable/disable features in LTAGE
Pau Cabre
2018-11-28
cpu: Added new stats to TAGE and LTAGE branch predictors
Pau Cabre
2018-11-28
cpu: split LTAGE implementation into a base TAGE and a derived LTAGE
Pau Cabre
2018-11-22
cpu: Made LTAGE parameters configurable
Pau Cabre
2018-11-22
cpu: Fixed useful counter handling in LTAGE
Pau Cabre
2018-11-22
cpu: Fixes on the loop predictor part of LTAGE
Pau Cabre
2018-11-17
cpu: Fix LTAGE max number of allocations on update
Pau Cabre
2018-11-17
configs: Added an option for choosing branch predictor type
Pau Cabre
2018-11-14
cpu: Fixed ratio of pred to hyst bits for LTAGE Bimodal
Pau Cabre
2018-11-13
cpu: Fixed PC shifting on LTAGE branch predictor
Pau Cabre
2017-12-04
misc: Rename misc.(hh|cc) to logging.(hh|cc)
Gabe Black
2017-09-06
cpu: Fix bi-mode branch predictor thresholds
Rico Amslinger
2016-11-09
style: [patch 1/22] use /r/3648/ to reorganize includes
Brandon Potter
2016-12-21
cpu: implement an L-TAGE branch predictor
Arthur Perais
2016-12-21
cpu: disallow speculative update of branch predictor tables (o3)
Arthur Perais
2016-12-21
cpu: correct comments in tournament branch predictor
Arthur Perais
2016-11-30
cpu: Remove branch predictor function predictInOrder
Jason Lowe-Power
2016-06-06
stats: Fixing regStats function for some SimObjects
David Guillen Fandos
2016-04-05
cpu: Implement per-thread GHRs
Mitch Hayenga
2016-04-05
cpu: Add an indirect branch target predictor
Mitch Hayenga
2016-04-05
cpu: Fix BTB threading oversight
Mitch Hayenga
2016-04-06
Revert power patch sets with unexpected interactions
Andreas Sandberg
2016-04-05
cpu: Implement per-thread GHRs
Curtis Dunham
2016-04-05
cpu: Add an indirect branch target predictor
Mitch Hayenga
2016-04-05
cpu: Fix BTB threading oversight
Mitch Hayenga
2016-02-06
style: fix missing spaces in control statements
Steve Reinhardt
2016-01-11
scons: Enable -Wextra by default
Andreas Hansson
2015-10-12
misc: Add explicit overrides and fix other clang >= 3.5 issues
Andreas Hansson
2015-10-12
misc: Remove redundant compiler-specific defines
Andreas Hansson
2015-09-15
cpu: pred: Local Predictor Reset in Tournament Predictor
Andrew Lukefahr
2015-04-13
cpu: re-organizes the branch predictor structure.
Dibakar Gope
2014-10-16
cpu: Add branch predictor PMU probe points
Andreas Sandberg
2014-09-27
arch: Use const StaticInstPtr references where possible
Andreas Hansson
2014-09-03
cpu: fix bimodal predictor to use correct global history reg
Dam Sunwoo
2014-09-03
cpu: Fix incorrect speculative branch predictor behavior
Mitch Hayenga
2014-08-13
scons: Build the branch predictor for all CPUs
Andreas Sandberg
2014-08-13
cpu: Modernise the branch predictor (STL and C++11)
Andreas Hansson
2014-07-23
cpu: `Minor' in-order CPU model
Andrew Bardsley
[next]