gem5 - gem5

Age	Commit message (Expand)	Author
2019-08-21	arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0	Ciro Santilli
2019-05-30	cpu-o3: Add support for pinned writes	Giacomo Gabrielli
2019-03-14	cpu: Refactor of Physical Register implementation	Andrea Mondelli
2019-01-30	arch,cpu: Add vector predicate registers	Giacomo Gabrielli
2018-09-13	Fix SConstruct for asan build	Earl Ou
2018-08-10	cpu: Add hash functionality for RegId class	Bradley Wang
2018-08-10	cpu: Removed unnecessary file reg_class_impl.hh	Bradley Wang
2017-07-05	cpu: Added interface for vector reg file	Rekai Gonzalez-Alberquilla
2017-07-05	cpu: Simplify the rename interface and use RegId	Rekai Gonzalez-Alberquilla
2017-07-05	arch, cpu: Architectural Register structural indexing	Nathanael Premillieu
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-10-15	cpu: rename _DepTag constants to _Reg_Base	Steve Reinhardt
2013-10-15	cpu: clean up architectural register classification	Steve Reinhardt