gem5 - gem5

Age	Commit message (Expand)	Author
2018-09-12	cpu: Replace the fastmem with a new CPU model	Andreas Sandberg
2014-09-20	cpu: use probes infrastructure to do simpoint profiling	Dam Sunwoo
2013-04-22	cpu: generate SimPoint basic block vector profiles	Dam Sunwoo
2013-02-15	cpu: Add CPU metadata om the Python classes	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-04-03	Atomic: Remove the physmem_port and access memory directly	Andreas Hansson
2012-02-13	MEM: Introduce the master/slave port roles in the Python classes	Andreas Hansson
2012-01-17	CPU: Moving towards a more general port across CPU models	Andreas Hansson
2011-02-03	Config: Keep track of uncached and cached ports separately.	Gabe Black
2009-09-22	python: Move more code into m5.util allow SCons to use that code.	Nathan Binkert
2008-08-19	CPU: Get rid of two more duplicated CPU params.	Gabe Black
2008-08-18	Changed BaseCPU::ProfileEvent's interval member to be of type Tick. This was ...	Richard Strong
2008-08-11	params: Convert the CPU objects to use the auto generated param structs.	Nathan Binkert
2008-06-18	AtomicSimpleCPU: Separate data stalls from instruction stalls.	Nathan Binkert
2007-11-12	X86: Implement a page table walker.	Gabe Black
2007-08-08	Added fastmem option.	Vincentius Robby
2007-05-27	Move SimObject python files alongside the C++ and fix	Nathan Binkert