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path: root/src/cpu/simple/atomic.cc
AgeCommit message (Expand)Author
2007-08-26Merge with headGabe Black
2007-08-26Simple CPU: Don't trace instructions that fault. Otherwise they show up twice.Gabe Black
2007-08-26Simple CPU: Added code that will split requests that cross block boundaries i...Gabe Black
2007-08-26Simple CPU: Make sure only instructions which complete without faulting are c...Gabe Black
2007-08-26Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.Gabe Black
2007-08-08Added fastmem option.Vincentius Robby
2007-08-04SimpleCPU: Add some DPRINTFsNathan Binkert
2007-07-29Merge Gabe's changes from head.Steve Reinhardt
2007-07-28Turn the instruction tracing code into pluggable sim objects.Gabe Black
2007-07-28AtomicSimpleCPU: fix inadvertent loss of endian conversion on read.Steve Reinhardt
2007-07-26Merge python and x86 changes with cache branchNathan Binkert
2007-07-23Major changes to how SimObjects are created and initialized. Almost allNathan Binkert
2007-06-30Make CPU models use new LoadLockedReq/StoreCondReq commands.Steve Reinhardt
2007-06-30Event descriptions should not end in "event"Steve Reinhardt
2007-06-30Get rid of Packet result field. Error responses areSteve Reinhardt
2007-06-19Make branches work by repopulating the predecoder every time through. This is...Gabe Black
2007-06-12Make microOp vs microop and macroOp vs macroop capitilization consistent.Gabe Black
2007-05-18Changes to make simple cpu handle pcs appropriately for x86Gabe Black
2007-04-10Even if you don't want to fetch more bytes, make sure you handle a fault.Gabe Black
2007-03-15Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
2007-03-15Make the predecoder an object with it's own switched header file. Start addin...Gabe Black
2007-03-11Make sttw and sttwa use the twin memory operations.Gabe Black
2007-03-09Two fixes:Kevin Lim
2007-03-02make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way a...Ali Saidi
2007-02-12some forgotten commitsAli Saidi
2007-02-12Merge zizzer:/bk/newmemAli Saidi
2007-02-12rename store conditional stuff as extra data so it can be used for conditiona...Ali Saidi
2007-02-12Move store conditional result checking from SimpleAtomicCpu writeSteve Reinhardt
2007-02-07Make memory commands dense again to avoid cache stat table explosion.Steve Reinhardt
2007-01-16Modify ISA and staticInst to support a IsFirstMicroOp flagAli Saidi
2006-12-04More changes to get SPARC fs closer. Now at 1.2M cycles before differenceAli Saidi
2006-11-29Merge zizzer:/bk/newmemAli Saidi
2006-11-29Add support for mmapped iprs to atomic cpuAli Saidi
2006-11-29Change the connecting of the physPort and virtPort to the memory object below...Kevin Lim
2006-11-17Make an initialization pass for the thread context and set the [phys,virt]Por...Ron Dreslinski
2006-11-14Make cpu's capable of having a phase shiftRon Dreslinski
2006-11-13Changes needed for a bus from CPU->L1Ron Dreslinski
2006-11-13Make CPU models signal to update the snoop rangesRon Dreslinski
2006-11-12Merge ktlim@zamp:./local/clean/tmp/test-regressKevin Lim
2006-11-11Get rid of the ParamContext for pseudo instructions and moveNathan Binkert
2006-11-09Draining fixes.Kevin Lim
2006-11-06Clean up clock phase drift code a bit.Kevin Lim
2006-11-01Merge zizzer.eecs.umich.edu:/bk/newmem/Gabe Black
2006-10-31Merge ktlim@zizzer:/bk/newmemKevin Lim
2006-10-31Remove mem parameter. Now the translating port asks the CPU's dcache's peer ...Kevin Lim
2006-10-31Put the Alpha tlb stuff into the AlphaISA namespace, and give the classes mor...Gabe Black
2006-10-28One last adjustment to get rid of skew in the simple atomic cpu.Gabe Black
2006-10-27A more complete attempt to fix the clock skew.Gabe Black
2006-10-27Potential fix to clock skew problem.Gabe Black
2006-10-23Merge zizzer:/bk/newmemLisa Hsu
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