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path: root/src/cpu/simple/atomic.cc
AgeCommit message (Expand)Author
2018-09-12cpu: Replace the fastmem with a new CPU modelAndreas Sandberg
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
2018-05-29cpu: Avoid unnecessary dynamic_pointer_cast in atomic modelGiacomo Travaglini
2017-12-13arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.Gabe Black
2017-12-05cpu: Add support for CMOs in the cpu modelsNikos Nikoleris
2017-11-21cpu, cpu, sim: move Cycle probe updateJose Marinho
2017-11-20pwr: Adds logic to enter power gating for the cpu modelAnouk Van Laer
2017-07-12cpu: Refactor some Event subclasses to lambdasSean Wilson
2015-07-20syscall_emul: [patch 13/22] add system call retry capabilityBrandon Potter
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-06-06pwr: Low-power idle power state for idle CPUsDavid Guillen Fandos
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
2016-04-06Revert power patch sets with unexpected interactionsAndreas Sandberg
2016-04-05mem: Remove threadId from memory request classMitch Hayenga
2014-12-09power: Low-power idle power state for idle CPUsAkash Bagdia
2015-07-19cpu: Fix LLSC atomic CPU wakeupKrishnendra Nathella
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2016-01-17cpu. arch: add initiateMemRead() to ExecContext interfaceSteve Reinhardt
2015-09-30cpu,isa,mem: Add per-thread wakeup logicMitch Hayenga
2015-09-30cpu: Add per-thread monitorsMitch Hayenga
2015-09-30config,cpu: Add SMT support to Atomic and Timing CPUsMitch Hayenga
2015-07-07sim: Refactor and simplify the drain APIAndreas Sandberg
2015-04-03cpu: fix system total instructions accountingNikos Nikoleris
2015-03-23mem: rename Locked/LOCKED to LockedRMW/LOCKED_RMWSteve Reinhardt
2015-02-11mem: restructure Packet cmd initialization a bit moreSteve Reinhardt
2015-01-25sim: Clean up InstRecordAli Saidi
2015-01-20cpu: commit probe notification on every microop or macroopNikos Nikoleris
2014-12-05cpu: Only check for PC events on instruction boundaries.Gabe Black
2014-12-02mem: Add const getters for write packet dataAndreas Hansson
2014-11-14arm: Fixes based on UBSan and static analysisAndreas Hansson
2014-11-06x86 isa: This patch attempts an implementation at mwait.Marc Orr
2014-10-16cpu: Probe points for basic PMU statsAndreas Sandberg
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-20cpu: use probes infrastructure to do simpoint profilingDam Sunwoo
2014-05-13mem: Refactor assignment of Packet typesCurtis Dunham
2014-01-24cpu: Add support for instructions that zero cache lines.Ali Saidi
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2014-01-24mem: per-thread cache occupancy and per-block agesDam Sunwoo
2014-01-24cpu: remove faulty simpoint basic block inst count assertionDam Sunwoo
2013-08-19cpu: Accurately count idle cycles for simple cpuLena Olson
2013-07-18mem: Set the cache line size on a system levelAndreas Hansson
2013-04-22cpu: generate SimPoint basic block vector profilesDam Sunwoo
2013-02-15sim: Add a system-global option to bypass cachesAndreas Sandberg
2013-02-15cpu: Refactor memory system checksAndreas Sandberg
2013-01-07cpu: Unify the serialization code for all of the CPU modelsAndreas Sandberg
2013-01-07cpu: Make sure that a drained atomic CPU isn't executing ucodeAndreas Sandberg
2013-01-07cpu: Rename defer_registration->switched_outAndreas Sandberg
2013-01-07cpu: Correctly call parent on switchOut() and takeOverFrom()Andreas Sandberg